Abstract: A plasma display device and a driving method thereof reduce the number of power supplies by generating each of different levels of voltages from one power supply using a voltage converter. The plasma display device comprises: a plasma display panel formed with a plurality of electrodes including a scan electrode; and a scan electrode driver for applying to a scan electrode a scan signal including a ramp pulse applied for a reset period. The scan electrode driver comprises: a power supply for applying a first voltage; a first supplying part coupled between the power supply and the plasma display panel for applying a first voltage of the power supply to the scan electrode; and a second supplying part connected in parallel to the first supplying part for generating a second voltage using the first voltage, and for applying to the scan electrode a third voltage which is increased by as much as the second voltage on the basis of the first voltage.

Abstract: A scan electrode driver for a plasma display device may include a set up voltage source that outputs a set up voltage, a rising ramp waveform generator that generates a rising ramp waveform in response to the set up voltage received from the set up voltage source and applies the rising ramp waveform to the plasma display panel, and a block unit arranged between the rising ramp waveform generator and one of the set up voltage source and the plasma display panel.

Abstract: An apparatus configured to drive a display panel by applying voltages of one or more levels to each of a plurality of electrode lines is disclosed. The apparatus includes first control switches configured to control a connection between a power source of a first level and each of the electrode lines and second control switches configured to control a connection between a power source of a second level and each of the electrode lines, wherein, when the power supply voltage of the first level or the second level is applied to the electrode lines, the electrode lines are divided into two or more groups, and the first control switches and the second control switches have different switching times according to the group to which they belong.

Abstract: A plasma display device that diversifies heat dissipating paths of integrated circuit modules in a circuit board assembly, thereby enhancing heat dissipation of the integrated circuit modules. The plasma display device includes a plasma display panel, a chassis base on which the plasma display panel is attached and supported, integrated circuit modules that are mounted on the circuit board assembly on an opposite side of the chassis base to the plasma display panel, and heat sinks, each being attached to one side of each of the integrated circuit modules to dissipate heat therefrom. The heat sink is formed such that one end thereof extends to come in contact with the chassis base.

Abstract: In a plasma display, a first electrode and a second electrode of a transistor may be respectively coupled to a scan electrode and a power source for supplying a scan voltage. The plasma display may include a scan electrode, a first transistor, a first resistor, and a second resistor. The first transistor may include a first electrode electrically coupled to the scan electrode, a second electrode electrically coupled to the power source and a control electrode. The first resistor may be electrically coupled between the scan electrode and the control electrode of the first transistor. The second resistor may be electrically coupled between the control electrode of the transistor and the power source.

Abstract: A plasma display device that diversifies heat dissipating paths of integrated circuit modules in a circuit board assembly, thereby enhancing heat dissipation of the integrated circuit modules. The plasma display device includes a plasma display panel, a chassis base on which the plasma display panel is attached and supported, integrated circuit modules that are mounted on the circuit board assembly on an opposite side of the chassis base to the plasma display panel, and heat sinks, each being attached to one side of each of the integrated circuit modules to dissipate heat therefrom. The heat sink is formed such that one end thereof extends to come in contact with the chassis base.

Abstract: Provided is a digital photographing apparatus in which information regarding a file to be deleted is moved to a temporary storage folder of a file storage unit and the file storage capacity of the temporary storing folder is displayed. Files in a digital photographing apparatus are managed by moving information regarding at least one file to be deleted to a temporary storage folder of a file storage unit, and deleting files of the temporary storage folder from the file storage unit.

Abstract: A method of managing files of a digital photographing apparatus and a digital photographing apparatus performing the file management method are provided. The file management method includes: photographing an image in a photographing mode, playing back stored image files in a playback mode, selecting an image file to be deleted according to a manipulation by a user in the playback mode, and deleting the image file from a storage medium after the playback mode is changed to the photographing mode.

Abstract: A thin film transistor is provided that includes a substrate, a gate electrode formed on the substrate, and a gate insulating layer formed all over the substrate including the gate electrode. A first semiconductor layer is formed on the gate insulating layer, and a second semiconductor layer is formed on the first semiconductor layer. Source and drain electrodes are separately etched together to expose a prescribed portion surface of the second semiconductor layer over the gate electrode. The source and drain electrodes adjacent to the prescribed portion of the second semiconductor layer are non-linearly inclined at their edges. A method of fabricating a thin film transistor includes forming a gate electrode on a substrate; forming a gate insulating layer on the gate electrode and the substrate, forming a first semiconductor layer on the gate insulating layer and forming a second semiconductor layer on the first semiconductor layer.

Abstract: A thin film transistor is provided that includes a substrate, a gate electrode formed on the substrate, and a gate insulating layer formed all over the substrate including the gate electrode. A first semiconductor layer is formed on the gate insulating layer, and a second semiconductor layer is formed on the first semiconductor layer. Source and drain electrodes are separately etched together to expose a prescribed portion surface of the second semiconductor layer over the gate electrode. The source and drain electrodes adjacent to the prescribed portion of the second semiconductor layer are non-linearly inclined at their edges. A method of fabricating a thin film transistor includes forming a gate electrode on a substrate; forming a gate insulating layer on the gate electrode and the substrate, forming a first semiconductor layer on the gate insulating layer and forming a second semiconductor layer on the first semiconductor layer.

Abstract: A thin film transistor is provided that includes a substrate, a gate electrode formed on the substrate, and a gate insulating layer formed all over the substrate including the gate electrode. A first semiconductor layer is formed on the gate insulating layer, and a second semiconductor layer is formed on the first semiconductor layer. Source and drain electrodes are separately etched together to expose a prescribed portion surface of the second semiconductor layer over the gate electrode. The source and drain electrodes adjacent to the prescribed portion of the second semiconductor layer are non-linearly inclined at their edges. A method of fabricating a thin film transistor includes forming a gate electrode on a substrate; forming a gate insulating layer on the gate electrode and the substrate, forming a first semiconductor layer on the gate insulating layer and forming a second semiconductor layer on the first semiconductor layer.