Abstract: A virtual channel DRAM arrangement is provided which can improve cell efficiency, reduce a layout area of a chip and increase a data processing speed, by unifying a data processing method.

Abstract: The circuit for controlling a sense amplifier according to the present invention can operate plurality of sense amplifiers groups selectively by controlling a bi-directional address signal for transferring data to the output buffer, an output buffer control signal for controlling the type of the data to be outputted into 8 byte, 16 byte etc., a sense amplifier enable signal for enabling the sense amplifier, and an erasure enable signal, therefore, the present invention can minimize a number of the sense amplifier groups, thereby reducing the power consumption and implementing a low power device.

Abstract: The present invention discloses a negative voltage drive circuit which does not takes an influence from the load capacitor or the power supply voltage drive circuit according to the present invention comprises a cross pumping circuit, a pumping unit block and circuit for supplying VCC or VSS power supply voltages for the pumping unit block.

Abstract: The present invention provides a flash memory device wherein memory cells in each of the memory cell blocks are divided into a plurality of memory cell groups. In each memory cell group, local bit lines are laid out connected by segmentation transistors. When selecting a memory cell, only a local bit line connected to a memory cell selected by an operation of the segmentation transistor is coupled to a global bit line so that the load to be applied to the bit lines is minimized during the read out operation.