Abstract: A charge or carrier injection transistor including a substrate, a gate electrode and an electric potential barrier layer forming an electric potential barrier against charges (either holes or electrons) injected by the gate electrode towards the substrate. A source and a drain are formed in the substrate on opposite sides of the gate electrode. A conduction channel, between the source and the drain, is formed on the substrate by charges passing through the electric potential barrier by a voltage applied to the gate electrode. When the applied voltage is removed, this channel disappears. That is, the transistor is ON when the charges from the gate electrode pass through the electric potential barrier and is OFF when no charges pass through it, thereby the charges perform a transistor switching function.

Abstract: A semiconductor device comprising a semiconductor substrate, an insulation structure formed on the substrate and including a groove extending along a top surface of the insulation structure, and a wiring film formed lengthwise on the groove of the insulation film.

Abstract: A multilayer interconnection structure for a semiconductor device improving the integration degree of the semiconductor device and reducing the contact resistance. This interconnection structure comprises a lower interconnection layer having a predetermined constant width, an insulating layer provided on the lower interconnection layer and having a contact hole which is vertically placed on the lower interconnection layer and has a width larger than that of the lower interconnection layer, and an upper interconnection layer laid on the insulating layer such that it is connected to the lower interconnection layer through the contact hole. The upper interconnection layer has an enlarged portion at each side of or at only a side of its section corresponding to the contact hole. The enlarged portion extends toward a longitudinal direction of the lower interconnection layer.

Abstract: A method for fabricating a semiconductor memory, including the steps of: forming a memory cell transistor having a gate electrode, a source area and a drain area on a semiconductor substrate; forming an insulating film over the memory cell transistor; forming an etch preventing film over the insulating film; forming multi-layer films over the etch preventing film by stacking alternately a disposable film and a conduction layer; selectively etching the multi-layer films corresponding to a contact hole to form a stacked film pattern; forming conductive sidewalls on sides of the stacked film pattern; forming a photoresist pattern on the stacked film pattern; selectively etching the etch preventing film and the insulating film by using the photoresist pattern and the conductive sidewall, and thereby forming the contact hole; forming an upper conductive film on the stacked film pattern and the contact hole including the conductive sidewall; patterning the upper conductive film and the stacked film pattern to there

Abstract: An isolation structure of a semiconductor device including a channel stop diffusion region selectively formed on a portion of a single crystalline silicon substrate disposed beneath an edge of a field oxide film formed on the substrate, thereby capable of selectively increasing, irrespective of a pattern size of the field region, a channel ion concentration at an edge of a field region where the field region is connected to an active region and which region is a weak area serving to decrease a channel stop ion concentration at an interface between the field oxide film and the silicon substrate and to decrease a threshold voltage of a field transistor due to a small thickness thereof and thereby locally increasing the threshold voltage. By the local increase in threshold voltage, it is possible to prevent a degradation in insulating characteristic of the field transistor with a small pattern size.

Abstract: A semiconductor memory device including a plurality of memory cells arranged in a matrix manner, each of the memory cells including a transfer transistor constituted by a gate electrode, a gate insulating film, a source region and a drain region, and a charge storage capacitor constituted by a storage node, a dielectric film and a plate electrode, the storage node of the charge storage capacitor including a cylindrical lower electrode formed above the transfer transistor via an insulating layer formed on the transfer transistor and connected to one of the source region and the drain region of the transfer transistor, and a cover type upper electrode formed on the lower electrode and connected with the lower electrode.

Abstract: A method for fabricating a semiconductor memory, including the steps of: forming transistors on a semiconductor substrate (100); forming a first insulation film (23, 24, 25) on the semiconductor substrate; forming contact holes by selectively etching the first insulation film; forming successively a first conductive layer (26), an etch preventing film (27), and a first temporary film (28) on the substrate and the contact holes; etching the first temporary film and the etch preventing film to selectively expose the first conduction layer; forming a second temporary film (30) on the first temporary film and the first conductive layer; etching the second temporary film to form sidewall spacers of the second temporary film at sidewalls of the first temporary film; patterning the first conduction film using the first temporary film and the sidewall spacers as masks; forming a second insulation film (31) on the first conductive layer, the sidewall spacers and the first temporary film; etching the second insulation

Abstract: A method for the fabrication of semiconductor device includes the steps of forming a first wiring layer on an insulating film overlaying a semiconductor substrate, depositing an interlayer insulating film entirely on the first wiring layer, etching the interlayer insulating film selectively to form a contact hole exposing the first wiring layer therethrough, forming a metal film on the interlayer insulating film and in the contact hole, etching the metal film selectively to leave the metal film only around the contact hole, depositing a mid-insulating film on the remaining metal film and on the interlayer insulating film applying annealing to the metal film to form a metal plug in the contact hole, the metal film filling the contact hole, removing the mid-insulating film and forming a second wiring layer on the interlayer insulating film and on the metal plug.

Abstract: A method of making a semiconductor device capable of simplifying the overall manufacturing processes and carrying out the reliable interconnections between wires.

Abstract: Methods of hyperfine patterning and manufacturing semiconductor devices. Steps in accordance with the present invention include coating a hemisphere particle layer having hills and valleys on a layer to be etched, the hemisphere particle layer having an etch selectivity higher than that of the first layer, filling the valleys of the hemisphere particle layer with a second layer having an etch selectivity higher than that of the hemisphere particle layer, and etching back the hills of the hemisphere particle layer to expose the first layer by using the second layer as a mask, and etching the first layer. By virtue of the hemisphere particle layer having alternating hills and valleys, it is possible to accomplish a hyperfine patterning of about 0.1 .mu.m. Since the mean size and the density of hills and valleys of the hemisphere layer can be controlled, the pattern size also can be controlled.

Abstract: This invention relates to a method for fabricating a semiconductor memory device with a large capacitance, which comprises the steps of forming a gate insulating film, a gate electrode and a source and drain region on a semiconductor substrate, forming an interlayer and an etch stopper on the whole surface, etching selectively away the etch stopper and the interlayer to form an opening, forming a first conductive layer, a first insulating film and a second insulating film on the whole surface, etching selectively away the first and second insulating film, forming a side wall spacer of a third insulating film on the side of the first and second insulating film, forming a fourth insulating film on the whole surface, etching selectively away the fourth insulating film, removing the second insulating film and the side wall spacer, forming a second conductive layer on the whole surface, etching selectively away the second conductive layer and the first insulating film and the first conductive layer, removing the f

Abstract: The invention relates to a semiconductor memory device in which a bit line ring which functions as a bit line is formed at the upper and lower stage of the bit line and a storage node is formed to be overlapped in the same direction with said bit line formed perpendicularly to a word line to improve the integration degree.Therefore, a capacitor area can be increased without an increase of an area of the unit cell to improve the integration degree of a semiconductor memory device and the generation of the bent portion of the active region can be avoided to decrease the distortion.

Abstract: A method of making a semiconductor memory device wherein a storage node having a plurality of pillars, capable of increasing the storage node surface area and thus the cell capacitance. The storage node is formed by depositing a storage node polysilicon film to have a thickness of 5,000 .ANG. to 6,000 .ANG. over a semiconductor substrate, forming a photoresist pattern over the polysilicon film in a direct electron beam writing manner, and etching the polysilicon film up to a depth of 1,000 .ANG. from the upper surfaces of a gate and a bit line by using the photoresist pattern. The formed storage node has a plurality of uniformly spaced pillars.

Abstract: A semiconductor memory cell and device having a tubular formed storage electrode of a capacitor through which a bit line passes. The source, gate and drain of a switching transistor are arranged in a direction parallel to a longitudinal axis of the tubular storage electrode. An active region also is arranged in a parallel or superposing direction relative to the bit line and in a perpendicular direction relative to the word line. A manufacturing method thereof includes forming a switching transistor, forming a part of the capacitor storage electrode connected with the drain of the switching transistor, forming an oxide film side wall, forming a bit line in parallel to a longitudinal axis of the active region, forming a capacitor storage electrode of tubular form, covering the surface of the capacitor storage electrode with a capacitor dielectric film, and forming a plate electrode of the capacitor thereon.

Abstract: The invention relates to a semiconductor memory device in which a bit line ring which functions as a bit line is formed at the upper and lower stage of the bit line and a storage node is formed to be overlapped in the same direction with said bit line formed perpendicularly to a word line to improve the integration degree.Therefore, a capacitor area can be increased without an increase of an area of the unit cell to improve the integration degree of a semiconductor memory device and the generation of the bent portion of the active region can be avoided to decrease the distortion.

Abstract: A method for forming an isolation region in a semiconductor device using a trench comprising the steps of forming a reaction restraining layer on a semiconductor substrate, removing a portion of the reaction restraining layer corresponding to a trench region for providing an isolation region, forming a reaction film on the entire exposed surface, heat treating the reaction film and the substrate, to form a reaction product film having a predetermined depth in a portion of the reaction film and a portion of the substrate corresponding to said trench region, etching and removing the reaction product film, to form a trench, forming an insulation film for the isolation region such that it fills sufficiently the trench, forming a surface smoothing insulation film on the insulation film for the isolation region, etching back both the insulation films such that their portions located above a predetermined height from the surface of the substrate are removed, and removing the remaining reaction restraining layer.

Abstract: Methods of hyperfine patterning and manufacturing semiconductor devices. Steps in accordance with the present invention include coating a hemisphere particle layer having hills and valleys on a layer to be etched, the hemisphere particle layer having an etch selectivity higher than that of the first layer, filling the valleys of the hemisphere particle layer with a second layer having an etch selectivity higher than that of the hemisphere particle layer, and etching back the hills of the hemisphere particle layer to expose the first layer by using the second layer as a mask, and etching the first layer. By virtue of the hemisphere particle layer having alternating hills and valleys, it is possible to accomplish a hyperfine patterning of about 0.1 .mu.m. Since the mean size and the density of hills and valleys of the hemisphere layer can be controlled, the pattern size also can be controlled.

Abstract: A method of making a semiconductor memory element such as in dynamic random access memories including forming a transistor on a semiconductor substrate, forming a polysilicon film, a metal silicide film and an oxide film, in this order, over the resultant entire exposed surface so as to form a bit line at the bit line contact, forming another oxide film over the resultant entire exposed surface and forming side wall spacers and a capacitor contact, depositing a first doped polysilicon film over the resultant entire exposed surface, and forming a first smoothing oxide film over the first doped polysilicon film. Over the resultant entire exposed surface, a nitride film is formed which has a thickness larger than that of the first doped polysilicon film by two times or more. A second smoothing oxide film is formed over the nitride film. The nitride film is etched using the smoothing oxide films as a mask.

Abstract: The present invention relates to a method for forming an isolated film on a semiconductor device in the shape of a cylinder to shorten the heat treatment process and to prevent a micro-loading effect of filling of a field-isolated oxide film. The method comprises the step of forming a deep, narrow groove, then filling up the groove with an oxide film, and then oxidizing a polysilicon layer encircled by the groove to form an isolated film in the shape of a cylinder.

Abstract: The present invention relates to a method for fabricating a semiconductor memory cell consisting of a switching transistor and a capacitor wherein a polysilicon pad and a polysilicon storage node are simultaneously patterned with a self-alignment method without a mask.Accordingly, the present invention has the following advantages: First, the overlay accuracy can be improved by patterning a polysilicon pad and a polysilicon storage node with a self-alignment method. Second, the fabrication process can be simpler than the prior fabrication process for the semiconductor memory cell of a noble stacked capacitor cell structure. Third, the storage capacitance of a capacitor can be increased.