Abstract: A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device configured to store data in a non-volatile state; and a controller configured to control the non-volatile memory device. The controller calculates a new performance level, compares the calculated performance level with a predetermined reference, and determines the calculated performance level as an updated performance level according to the comparison result.

Abstract: A memory device includes a plurality of memory chips, including one or more memory chips that store authentication information, and a controller including a first register that stores information indicating a representative memory chip, from among the one or more memory chips that store the authentication information, that stores valid authentication information.

Abstract: A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device configured to store data in a non-volatile state; and a controller configured to control the non-volatile memory device. The controller calculates a new performance level, compares the calculated performance level with a predetermined reference, and determines the calculated performance level as an updated performance level according to the comparison result.

Abstract: A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device configured to store data in a non-volatile state, and a controller configured to control the non-volatile memory device. The controller calculates a new performance level, compares the calculated performance level with a predetermined reference, and determines the calculated performance level as an updated performance level according to the comparison result.

Abstract: A semiconductor storage device (SSD) and a method of throttling performance of the SSD are provided. The method can include includes gathering at least two workload data items related with to a workload of the semiconductor storage device, estimating the workload using the at least two workload data items, and throttling the performance of the semiconductor storage device according to the estimated workload. Accordingly, a workload that the semiconductor storage device will undergo can be estimated.

Abstract: A memory device includes a plurality of memory chips, including one or more memory chips that store authentication information, and a controller including a first register that stores information indicating a representative memory chip, from among the one or more memory chips that store the authentication information, that stores valid authentication information.

Abstract: A semiconductor memory device including a plurality of layers each including a memory cell array and which are stacked over each other; and at least one power plane for supplying power to the layers. The power plane includes a region to which a power voltage is applied and a region to which a ground voltage is applied. The region to which a power voltage is applied is located adjacent to the region to which a ground voltage is applied, and forms a decoupling capacitor therebetween to decouple an influx of power noise to the layers or generation of power noise in the layers.

Abstract: Phase-change and resistance-change random access memory devices are provided which include a phase-change or resistance-change memory cell array and a sense amplifier that is configured to amplify data read from the phase-change memory cell array. These random access memory devices are configured to read data from a first word line of the phase-change or resistance-change memory cell array and to insert a dummy burst in which no data is read when a first boundary crossing occurs during a burst mode operation. Related methods of operating phase-change and/or resistance-change random access memory devices in burst mode are also provided.

Abstract: A resistance variable memory device includes a resistance variable memory cell array, a data register that prefetches read data of the resistance variable memory cell array, a data output unit that receives the prefetched read data from the data register and outputs the received data, and a page mode setting unit that sets one of a first page mode and a second page mode as a page mode. In the first page mode, the data output unit sequentially reads the read data prefetched in the data register as page addresses are sequentially received, and in the second page mode, the data output unit sequentially reads the read data prefetched in the data register after a start page address among a plurality of page addresses has been received.

Abstract: A phase-change random access memory device is provided. The phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit, multiple local bit lines, each being connected to multiple phase-change memory cells, and multiple column select transistors selectively connecting the global bit line with each of the multiple local bit lines, each column select transistor having a resistance that varies depending on its distance from the write circuit and the read circuit.

Abstract: A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device configured to store data in a non-volatile state; and a controller configured to control the non-volatile memory device. The controller calculates a new performance level, compares the calculated performance level with a predetermined reference, and determines the calculated performance level as an updated performance level according to the comparison result.

Abstract: A semiconductor storage device (SSD) and a method of throttling performance of the SSD. The method can include gathering at least two workload data items related with a workload of the semiconductor storage device, estimating the workload using the at least two workload data items, and throttling the performance of the semiconductor storage device according to the estimated workload. Accordingly, a workload that the semiconductor storage device will undergo can be estimated.

Abstract: A semiconductor memory device including a plurality of layers each including a memory cell array and which are stacked over each other; and at least one power plane for supplying power to the layers. The power plane includes a region to which a power voltage is applied and a region to which a ground voltage is applied.

Abstract: A resistance-change random access memory device includes a resistance-change memory cell array having a plurality of resistance-change memory cells, where a plurality of word lines are connected to respective first terminals of the plurality of resistance-change memory cells. A plurality of bit lines are disposed perpendicular to the word lines and connected to respective second terminals of the plurality of resistance-change memory cells. The device also includes a plurality of discharge elements that are capable of connecting or disconnecting respective bit lines from a discharge voltage, where the discharge elements connect the respective bit lines to the discharge voltage before write and read operations.

Abstract: A phase-change random access memory (PRAM) device includes a PRAM cell array including a first sector and a second sector, a first global bit line coupled to a first local bit line of the first sector and a first local bit line of the second sector, and a first plurality of global bit line discharge units coupled to the first global bit line, the first plurality of global bit line discharge units configured to discharge the first global bit line in response to a first global discharge signal.

Abstract: Phase-change and resistance-change random access memory devices are provided which include a phase-change or resistance-change memory cell array and a sense amplifier that is configured to amplify data read from the phase-change memory cell array. These random access memory devices are configured to read data from a first word line of the phase-change or resistance-change memory cell array and to insert a dummy burst in which no data is read when a first boundary crossing occurs during a burst mode operation. Related methods of operating phase-change and/or resistance-change random access memory devices in burst mode are also provided.

Abstract: A resistance variable memory device includes a resistance variable memory cell array, a data register that prefetches read data of the resistance variable memory cell array, a data output unit that receives the prefetched read data from the data register and outputs the received data, and a page mode setting unit that sets one of a first page mode and a second page mode as a page mode.

Abstract: A resistance-change random access memory device includes a resistance-change memory cell array having a plurality of resistance-change memory cells, where a plurality of word lines are connected to respective first terminals of the plurality of resistance-change memory cells. A plurality of bit lines are disposed perpendicular to the word lines and connected to respective second terminals of the plurality of resistance-change memory cells. The device also includes a plurality of discharge elements that are capable of connecting or disconnecting respective bit lines from a discharge voltage, where the discharge elements connect the respective bit lines to the discharge voltage before write and read operations.

Abstract: A phase-change random access memory device is provided. The phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit, multiple local bit lines, each being connected to multiple phase-change memory cells, and multiple column select transistors selectively connecting the global bit line with each of the multiple local bit lines, each column select transistor having a resistance that varies depending on its distance from the write circuit and the read circuit.

Abstract: A phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit; a plurality of local bit lines, each of which being connected to a plurality of phase-change memory cells; and a plurality of column select transistors selectively connecting the global bit line with each of the plurality of local bit lines. Each column select transistor has a resistance that depends on distance from the write circuit and the read circuit.