Abstract: In one embodiment, a semiconductor package includes a circuit substrate, a plurality of semiconductor chips stacked on the circuit substrate, insulating adhesive patterns interposed between the semiconductor chips, a heat slug provided on an uppermost semiconductor chip and adhered to the uppermost semiconductor chip by a heat dissipative adhesive pattern, and a mold structure provided on the circuit substrate to cover sidewalls of the semiconductor chips, the insulating adhesive patterns, the heat dissipative adhesive pattern and the heat slug. A failure of the semiconductor package during a manufacturing process of the mold structure may be reduced. The semiconductor package may therefore have good operating characteristics and reliability.

Abstract: A semiconductor package includes a first semiconductor chip on a substrate and having a plurality of through-silicon vias (TSVs). A second semiconductor chip having an active layer is on the first semiconductor chip. An adhesive layer is between the first semiconductor chip and the active layer. Connection terminals extend through the adhesive layer and are connected to the TSVs and the active layer. Side surfaces of the adhesive layer are aligned with side surfaces of the second semiconductor chip.

Abstract: A method of manufacturing a semiconductor package includes preparing a parent substrate including package board parts laterally spaced apart from each other, mounting a first chip including a through-via electrode on each of the package board parts, forming a first mold layer on the parent substrate having the first chips, planarizing the first mold layer to expose back sides of the first chips, etching the exposed back sides of the first chips to expose back sides of the through-via electrodes, forming a passivation layer on the planarized first mold layer, the etched back sides of the first chips, and the back sides of the through-via electrodes, and selectively removing the passivation layer to expose the back sides of the through-via electrodes.

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip, and a connection member to electrically connect the first semiconductor chip and the second semiconductor chip. The connection member may include a connection pad disposed on the first semiconductor chip, a connection pillar disposed on the second semiconductor chip, and a bonding member to connect the connection pad and the connection pillar. An anti-contact layer may be formed on at least one surface of the connection pad.

Abstract: A method of manufacturing a semiconductor package includes preparing a parent substrate including package board parts laterally spaced apart from each other, mounting a first chip including a through-via electrode on each of the package board parts, forming a first mold layer on the parent substrate having the first chips, planarizing the first mold layer to expose back sides of the first chips, etching the exposed back sides of the first chips to expose back sides of the through-via electrodes, forming a passivation layer on the planarized first mold layer, the etched back sides of the first chips, and the back sides of the through-via electrodes, and selectively removing the passivation layer to expose the back sides of the through-via electrodes.

Abstract: A substrate of a semiconductor package includes a first wiring substrate having a first surface and a second surface facing each other, the first surface having a semiconductor chip mounted thereon, a first support carrier, and an adhesive film connecting the second surface and the first support carrier.

Abstract: Disclosed are methods of treating a device-substrate, and support-substrates used therein. The methods may include providing the device-substrate having an integrated circuit, bonding a first top surface of the device-substrate to a support-substrate, and polishing a first bottom surface of the device-substrate. The support-substrates include a second top surface, a second bottom surface opposite to the second top surface, and a sidewall connecting the second top and bottom surfaces. Additionally, the support-substrates further include a grooved portion spaced apart from the sidewall and blocking a crack in the support-substrates occurring from the sidewall.

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip, and a connection member to electrically connect the first semiconductor chip and the second semiconductor chip. The connection member may include a connection pad disposed on the first semiconductor chip, a connection pillar disposed on the second semiconductor chip, and a bonding member to connect the connection pad and the connection pillar. An anti-contact layer may be formed on at least one surface of the connection pad.

Abstract: Provided are semiconductor devices and methods of manufacturing the same. The semiconductor package includes a substrate, a first semiconductor chip mounted on the circuit substrate and having a first width, a second semiconductor chip overlying the first semiconductor chip and having a second width greater than the first width, and a first under filler disposed between the first and second semiconductor chips, covering a side surface of the first semiconductor chip and having an inclined side surface.

Abstract: A semiconductor package including connecting members having a controlled content ratio of gold capable of increasing durability and reliability by preventing an intermetallic compound having high brittleness from being formed. The semiconductor package includes a base substrate; a first semiconductor chip disposed on the base substrate; and a first connecting member for electrically connecting the base substrate and the first semiconductor chip, and comprising a first bonding portion that includes gold and has a first content ratio of gold that is controlled to prevent an intermetallic compound of AuSn4, (Cu, Au)Sn4, or (Ni, Au)Sn4 from being formed.

Abstract: Disclosed are via, a method for formation of via using zinc and zinc alloys, and a process for fabrication of three-dimensional multiple chip stack packages by using the same. In lamination of three-dimensional chips, the chips with reduced defects are rapidly formed by the steps of: punching each of the chips to form a via hole used for a circuit wiring between the chips; depositing a seed layer on an inside of the via hole; forming a plated layer inside the via hole by using Zn and Zn alloys through an electroplating process; removing oxide film from surface of the plated layer; and heat treating the via hole at a temperature of more than melting point of the Zn and Zn alloys. Particularly, the chip having Zn via formed according to the present invention has an advantage of simultaneously overcoming problems in establishment of processing parameters caused by Cu via (e.g., plating mode, current density, influence of additives, pore formation, etc.

Abstract: A method for bonding electronic components finished with electroless NiXP layer for preventing a brittle solder joint fracture is provided with the steps comprising: forming an electroless NiXP metal layer on a metal deposition of electronic components, wherein X is selected from the group consisting of W, Mo, Co, Ti, Zr, Zn, V, Cr, Fe, Nb, Re, Mn, Tl and Cu; and reflowing a lead-free solder on the electroless NiXP layer to be bonded. X element was suppressed the formation of Ni3P, Ni3SnP intermetallic compound and prevented the spalling behavior of Ni3Sn4. Therefore, solder joint reliability can be improved significantly.

Abstract: Disclosed are an integrated circuit chip package and a method of connecting an integrated circuit chip and an attachment subject to each other while interposing an adhesive therebetween. The connection between integrated circuit chip and the attachment subject stress often leads to component failure and the addition of an interface layer with a similar thermal expansion coefficient improves reliability. The method may include applying the adhesive on the attachment subject, forming an interface layer between the integrated circuit chip and the adhesive wherein the interface layer has a thermal expansion coefficient similar to a thermal expansion coefficient of the integrated circuit chip. By connecting an integrated circuit chip and the attachment subject to each other by an adhesive via the interface layer, the generation of delamination is minimized and reliability is improved.

Abstract: Disclosed is a method of joining electronic package parts, comprising the steps of: reflowing lead-free solders containing alloy elements on top of each of the electronic package parts having a surface treated with copper or nickel; and mounting the surface treated electronic parts on the lead-free solders then reflowing the lead-free solders to generate intermetallic compound between the lead-free solders and the surface treated portion of each of the electronic parts.