Abstract: An amorphous silicon thin film transistor, an organic light-emitting display (OLED) device including the same and method thereof are provided. The example amorphous silicon thin film transistor may include an amorphous silicon thin film transistor portion including a gate electrode, a gate insulating layer, an amorphous silicon layer, and source/drain electrodes and a heat generating portion generating heat and applying the heat to the amorphous silicon layer to reduce a threshold voltage of the amorphous silicon thin film transistor portion. The example method may include applying heat to an amorphous silicon layer if a threshold voltage of an amorphous silicon thin film transistor rises above a default level, the amorphous silicon thin film transistor including the amorphous silicon layer, the applied heat configured to reset the threshold voltage to the default level.

Abstract: A memory device and method for operating the same are provided. The example method may be directed to a method of performing a memory operation on a memory device, and may include applying a negative voltage bias to the memory device during a programming operation of the memory device and applying a positive voltage bias to the memory device during an erasing operation of the memory device. The example memory device may include a substrate and a gate structure formed on the substrate, the gate structure exhibiting a faster flat band voltage shift under a negative voltage bias than under a positive voltage bias, the gate structure receiving a negative voltage bias during a programming of the memory device and receiving a positive voltage bias during an erasing operation of the memory device.

Abstract: A semiconductor memory device having an alloy gate electrode layer and method of manufacturing the same are provided. The semiconductor memory device may include a semiconductor substrate having a first impurity region and a second impurity region. The semiconductor memory device may include a gate structure formed on the semiconductor substrate and contacting the first and second impurity regions. The gate structure may include an alloy gate electrode layer formed of a first metal and a second metal. The first metal may be a noble metal. The second metal may include at least one of aluminum (Al) and titanium (Ti), gallium (Ga), indium (In), tin (Sb), thallium (Tl), bismuth (Bi) and lead (Pb).

Abstract: Example embodiments may provide memory devices having a charge trap layer which includes a hole trap and an electron trap. The memory device may generate a relatively large flat band voltage gap according to an applied bias voltage. Accordingly, a stable multilevel cell may be realized.

Abstract: A memory device may include a switching device and a storage node coupled with the switching device. The storage node may include a first electrode, a second electrode, a data storage layer and at least one contact layer. The data storage layer may be disposed between the first electrode and the second electrode and may include a transition metal oxide or aluminum oxide. The at least one contact layer may be disposed at least one of above or below the data storage layer and may include a conductive metal oxide.

Abstract: A nonvolatile memory device including a nano dot and a method of fabricating the same are provided. The nonvolatile memory device may include a lower electrode, an oxide layer on the lower electrode, a nano dot in the oxide layer and an upper electrode on the oxide layer. In example embodiments, the current paths inside the oxide layer may be unified, thereby stabilizing the reset current.

Abstract: Example embodiments relate to a method of manufacturing amorphous NiO thin films and nonvolatile memory devices including amorphous thin films that use a resistance material. Other example embodiments relate to a method of manufacturing amorphous NiO thin films having improved switching and resistance characteristics by reducing a leakage current and non-volatile memory devices using an amorphous NiO thin film. Provided is a method of manufacturing an amorphous NiO thin film having improved switching behavior by reducing leakage current and improving resistance characteristics. The method may include preparing a substrate in a vacuum chamber, preparing a nickel precursor material, preparing a source gas by vaporizing the nickel precursor material, preparing a reaction gas, preparing a purge gas and forming a monolayer NiO thin film on the substrate by performing one cycle of sequentially supplying the source gas, the purge gas, the reaction gas and the purge gas into the vacuum chamber.

Abstract: A nano-elastic memory device and a method of manufacturing the same. The nano-elastic memory device may include a substrate, a plurality of lower electrodes arranged in parallel on the substrate, a support unit formed of an insulating material to a desired or predetermined thickness on the substrate having cavities that expose the lower electrodes, a nano-elastic body extending perpendicular from a surface of the lower electrodes in the cavities, and a plurality of upper electrodes formed on the support unit and perpendicularly crossing the lower electrodes over the nano-elastic bodies.

Abstract: Nonvolatile memory devices and methods of manufacturing the same are provided. The nonvolatile memory devices may include an oxide layer formed of a resistance conversion material, a lower electrode, a nano-wire layer formed of a transition metal on the lower electrode, and an upper electrode formed on the oxide layer. According to example embodiments, a reset current may be stabilized by unifying a current path on the oxide layer.

Abstract: A memory device with a silicon rich oxide layer and a method of manufacturing the same are provided. The memory device with a silicon rich oxide layer may include a semiconductor substrate, source/drain regions formed on the semiconductor substrate, and a gate structure formed on the semiconductor substrate. The gate structure may contact with the source/drain regions and may include a silicon oxide layer with a silicon content greater than that of a silicon oxide layer (SiO2).

Abstract: A nonvolatile memory device including a lower electrode, a resistor structure disposed on the lower electrode, a diode structure disposed on the resistor structure, and an upper electrode disposed on the diode structure. A nonvolatile memory device wherein the resistor structure includes one resistor and the diode structure includes one diode. An array of nonvolatile memory devices as described above.