Abstract: The present invention is intended to prevent shadow by a reflection plate, which may be generated according to a solar path variation, to increase a power generation efficiency of a solar cell module. To achieve the objects, one aspect of the present invention includes a solar cell panel and a reflection plate connected to and disposed on an edge of the solar cell pane, and angles between the reflection plates and a surface of the panel is simultaneously or individually varied.

Abstract: The present invention relates to a solar photovoltaic system suitably used for agriculture or used on water and including a reflector for reflecting sunlight. According to the present invention, a solar photovoltaic system includes a solar cell panel and a reflector spaced a predetermined distance from the solar cell panel. Here, at least a portion of a reflection surface of the reflector, which faces the solar cell panel, has a convexly curved surface.

Abstract: A photovoltaic cell module includes at least two unit modules, wherein each of the unit modules comprises at least one photovoltaic cell comprising a light absorbing layer and an electrode, and a power generation is performed in a state in which an own shape of the unit module or an arranged shape of two or more unit modules forms an uneven portion on an incident surface to which the sunlight is incident.

Abstract: A method for preparing a solar cell, includes: forming a first electrode on a substrate; forming a light absorbing layer on the first electrode; and forming a second electrode on the light absorbing layer, wherein the method further comprises forming an impurity material layer including an impurity element on the light absorbing layer adjacent to the first electrode or the second electrode in any one side or both sides thereof, and forming a doping layer by diffusing the impurity element into a portion of the light absorbing layer.

Abstract: The present invention relates to a structure of a solar cell for improving photoelectric conversion efficiency of the solar cell, and a manufacturing method therefor. One aspect of the solar cell according to the present invention relates to a solar cell having a light-absorbing layer formed between two electrodes arranged to face each other, wherein an electrical polarization layer comprising an electrical polarization material forming an inner electrical field is formed between the electrodes and the light-absorbing layer.

Abstract: A method for preparing a solar cell, includes: forming a first electrode on a substrate; forming a light absorbing layer on the first electrode; and forming a second electrode on the light absorbing layer, wherein the method further comprises forming an impurity material layer including an impurity element on the light absorbing layer adjacent to the first electrode or the second electrode in any one side or both sides thereof, and forming a doping layer by diffusing the impurity element into a portion of the light absorbing layer.

Abstract: A solar cell includes a light-absorbing layer, comprising a Cu compound or Cd compound, between two electrodes facing each other, has an impurity material layer, comprising an impurity element to be provided to the Cu compound or Cd compound, formed on any one side or both sides between the two electrodes and the light absorbing layer, and has a doping layer formed on one part of the light absorbing layer by means of the impurity element being diffused on the light absorbing layer.

Abstract: Disclosed is a solar cell including a substrate, a back electrode, a light-absorbing layer, a buffer layer, and a front transparent electrode. The buffer layer includes a titanium (Ti) compound. The light-absorbing layer includes a compound composed of M1, M2, M3 (where M1 is copper (Cu), silver (Ag), or a combination thereof, M2 is indium (In), gallium (Ga), aluminum (Al), zinc (Zn), tin (Sn), or a combination thereof, and M3 is selenium (Se), sulfur (S), or a combination thereof), and a combination thereof.

Abstract: The present invention relates to a structure of a solar cell for improving photoelectric conversion efficiency of the solar cell, and a manufacturing method therefor. One aspect of the solar cell according to the present invention relates to a solar cell having a light-absorbing layer formed between two electrodes arranged to face each other, wherein an electrical polarization layer comprising an electrical polarization material forming an inner electrical field is formed between the electrodes and the light-absorbing layer.

Abstract: A method for forming an isolation layer of a semiconductor device which is capable of improving isolation characteristics of a highly integrated semiconductor device. The method includes the steps of forming a first insulating layer on a substrate; forming both a first recess in the first isolation region and a plurality of second recesses in the second isolation region by only once applying a photolithography process to the first insulating layer; forming a third recess, which is deeper than the first recess, in the center area of the first recess in the first isolation region; and filling the first, second, third recesses with insulating materials or a thermal oxide layer. In addition, in the semiconductor device includes isolation regions have different widths, wherein the first isolation region, which is relatively narrower in width than the second isolation region, has a deeper recess than the second isolation region.

Abstract: A method for forming an isolation layer of a semiconductor device which is capable of improving isolation characteristics of a highly integrated semiconductor device. The method includes the steps of forming a first insulating layer on a substrate; forming both a first recess in the first isolation region and a plurality of second recesses in the second isolation region by only once applying a photolithography process to the first insulating layer; forming a third recess, which is deeper than the first recess, in the center area of the first recess in the first isolation region; and filling the first, second, third recesses with insulating materials or a thermal oxide layer. In addition, in the semiconductor device in which the isolation region has different widths, the first isolation region which is relatively narrower in width than the second isolation region has a deeper recess than the second isolation region.

Abstract: A method for forming an isolation layer of a semiconductor device which is capable of improving isolation characteristics of a highly integrated semiconductor device. The method includes the steps of forming a first insulating layer on a substrate; forming both a first recess in the first isolation region and a plurality of second recesses in the second isolation region by only once applying a photolithography process to the first insulating layer; forming a third recess, which is deeper than the first recess, in a center area of the first recess in the first isolation region; and filling the first, second, third recesses with insulating materials or a thermal oxide layer. In addition, the semiconductor device includes isolation regions have different widths, wherein the first isolation region, which is relatively narrower in width than the second isolation region, has a deeper recess than the second isolation region.

Abstract: A memory device and method of forming the same, includes a plurality of wordlines for applying a cell driving signal, a plurality of bitlines for inputting or outputting data, and a plurality of cells, each cell having a first gate, source and drain electrodes and a second gate, wherein either the first or second gate is connected to one of the wordlines, the source electrode is connected to one of the bitlines, and the drain electrode is connected to either the first or second gate which is not connected to the one wordline.

Abstract: A metal wiring stricture includes a conduction line, an insulator film for electrically insulating the conduction line, and a transmutation layer formed as the density of a portion of the insulator film adjacent to the conduction line is increased or by adding impurities to the insulator film. A metal wiring forming method for a semiconductor device, includes the step of forming a trench in a given portion of a silicon oxidation film formed on a semiconductor substrate, forming a transmutation layer on a surface of the silicon oxidation film, and depositing a conductive material on the transmutation layer to form a conduction line, whereby diffusion of the conductive material is prevented.

Abstract: A memory device and method of forming the same, includes a plurality of wordlines for applying a cell driving signal, a plurality of bitlines for inputting or outputting data, and a plurality of cells, each cell having a first gate, source and drain electrodes and a second gate, wherein either the first or second gate is connected to one of the wordlines, the source electrode is connected to one of the bitlines, and the drain electrode is connected to either the first or second gate which is not connected to the one wordline.

Abstract: A memory device and method of forming the same, includes a plurality of wordlines for applying a cell driving signal, a plurality of bitlines for inputting or outputting data, and a plurality of cells, each cell having a first gate, source and drain electrodes and a second gate, wherein either the first or second gate is connected to one of the wordlines, the source electrode is connected to one of the bitlines, and the drain electrode is connected to either the first or second gate which is not connected to the one wordline.

Abstract: A metal wire forming method for a semiconductor device includes the step of forming a first insulator film over a substrate having at least a second insulator film formed thereon and a first conductive layer formed on the second insulator film. Next, a photosensitive film is formed on the first insulator film, and the photosensitive film is exposed and developed according to a contact hole pattern. This exposes a portion of the first insulator film, and the exposed portion is then etched using the photosensitive film as a mask to form a contact hole in the first insulator film. The method further includes the steps of exposing and developing the photosensitive film according to a trench pattern which includes the contact hole pattern, and etching the first insulator film using the photosensitive film as the mask so that a trench having a predetermined depth is formed in the first insulator film and the first conductive layer is exposed via the contact hole.

Abstract: A metal wire and a method for forming a metal wire of a semiconductor device, including the steps of forming an insulating layer and first etch-stop layer on a substrate forming a first trench having sidewalls and a bottom by selectively removing portions of said first etch-stop layer forming a second etch-stop layer on the insulating layer, including the first trench, and first-etch stop layer etching back said second etch-stop layer from within the trench to form a mask from said first and second etch-layers exposing a portion of the trench bottom, wherein the width of the mask has a width of less than the width of the trench bottom etching the insulating layer using said first and second etch-stop layers mask to form a second trench extending through the insulating layer for holding a contact plug removing said first and second etch-stop layers and forming a contact plug and conductive layer in said first and second trenches.

Abstract: A wiring structure of a semiconductor device includes a substrate; a first conductive layer formed in the substrate; an insulation film formed on the substrate including the first conductive layer and having a contact hole therein through which the upper surface of the first conductive layer is exposed, wherein the contact hole includes an upper contact hole and a lower contact hole having a shape undercut into the insulation film and thus being wider than the upper contact hole; and a second conductive layer formed on the insulation film so as to thoroughly fill the contact hole and electrically connected to the first conductive layer.

Abstract: The DRAM cell includes a first transistor, a second transistor, and a capacitor. The first and second transistors each have a gate, a source, and a drain electrode. The gate electrode of the second transistor is connected to one of the source and drain electrodes of the first transistor, and a first electrode of the capacitor is connected to the gate electrode of the second transistor. Also, a second electrode of the capacitor is connected to one of the source and drain electrodes of the second transistor. One of the source and drain electrodes of the second transistor not connected to the second electrode of the capacitor is connected to the gate electrode of the second transistor. Accordingly, the second transistor is on when a logic value of "1" is stored in the gate thereof, and off when a logic value of `0` is stored in the gate thereof.