Abstract: The present invention relates to a structure of a solar cell for improving photoelectric conversion efficiency of the solar cell, and a manufacturing method therefor. One aspect of the solar cell according to the present invention relates to a solar cell having a light-absorbing layer formed between two electrodes arranged to face each other, wherein an electrical polarization layer comprising an electrical polarization material forming an inner electrical field is formed between the electrodes and the light-absorbing layer.

Abstract: Disclosed is a solar cell including a substrate, a back electrode, a light-absorbing layer, a buffer layer, and a front transparent electrode. The buffer layer includes a titanium (Ti) compound. The light-absorbing layer includes a compound composed of M1, M2, M3 (where M1 is copper (Cu), silver (Ag), or a combination thereof, M2 is indium (In), gallium (Ga), aluminum (Al), zinc (Zn), tin (Sn), or a combination thereof, and M3 is selenium (Se), sulfur (S), or a combination thereof), and a combination thereof.

Abstract: A method for forming an isolation layer of a semiconductor device which is capable of improving isolation characteristics of a highly integrated semiconductor device. The method includes the steps of forming a first insulating layer on a substrate; forming both a first recess in the first isolation region and a plurality of second recesses in the second isolation region by only once applying a photolithography process to the first insulating layer; forming a third recess, which is deeper than the first recess, in the center area of the first recess in the first isolation region; and filling the first, second, third recesses with insulating materials or a thermal oxide layer. In addition, in the semiconductor device includes isolation regions have different widths, wherein the first isolation region, which is relatively narrower in width than the second isolation region, has a deeper recess than the second isolation region.

Abstract: A method for forming an isolation layer of a semiconductor device which is capable of improving isolation characteristics of a highly integrated semiconductor device. The method includes the steps of forming a first insulating layer on a substrate; forming both a first recess in the first isolation region and a plurality of second recesses in the second isolation region by only once applying a photolithography process to the first insulating layer; forming a third recess, which is deeper than the first recess, in the center area of the first recess in the first isolation region; and filling the first, second, third recesses with insulating materials or a thermal oxide layer. In addition, in the semiconductor device in which the isolation region has different widths, the first isolation region which is relatively narrower in width than the second isolation region has a deeper recess than the second isolation region.

Abstract: A method for forming an isolation layer of a semiconductor device which is capable of improving isolation characteristics of a highly integrated semiconductor device. The method includes the steps of forming a first insulating layer on a substrate; forming both a first recess in the first isolation region and a plurality of second recesses in the second isolation region by only once applying a photolithography process to the first insulating layer; forming a third recess, which is deeper than the first recess, in a center area of the first recess in the first isolation region; and filling the first, second, third recesses with insulating materials or a thermal oxide layer. In addition, the semiconductor device includes isolation regions have different widths, wherein the first isolation region, which is relatively narrower in width than the second isolation region, has a deeper recess than the second isolation region.

Abstract: A metal wiring stricture includes a conduction line, an insulator film for electrically insulating the conduction line, and a transmutation layer formed as the density of a portion of the insulator film adjacent to the conduction line is increased or by adding impurities to the insulator film. A metal wiring forming method for a semiconductor device, includes the step of forming a trench in a given portion of a silicon oxidation film formed on a semiconductor substrate, forming a transmutation layer on a surface of the silicon oxidation film, and depositing a conductive material on the transmutation layer to form a conduction line, whereby diffusion of the conductive material is prevented.

Abstract: A metal wire and a method for forming a metal wire of a semiconductor device, including the steps of forming an insulating layer and first etch-stop layer on a substrate forming a first trench having sidewalls and a bottom by selectively removing portions of said first etch-stop layer forming a second etch-stop layer on the insulating layer, including the first trench, and first-etch stop layer etching back said second etch-stop layer from within the trench to form a mask from said first and second etch-layers exposing a portion of the trench bottom, wherein the width of the mask has a width of less than the width of the trench bottom etching the insulating layer using said first and second etch-stop layers mask to form a second trench extending through the insulating layer for holding a contact plug removing said first and second etch-stop layers and forming a contact plug and conductive layer in said first and second trenches.

Abstract: The DRAM cell includes a first transistor, a second transistor, and a capacitor. The first and second transistors each have a gate, a source, and a drain electrode. The gate electrode of the second transistor is connected to one of the source and drain electrodes of the first transistor, and a first electrode of the capacitor is connected to the gate electrode of the second transistor. Also, a second electrode of the capacitor is connected to one of the source and drain electrodes of the second transistor. One of the source and drain electrodes of the second transistor not connected to the second electrode of the capacitor is connected to the gate electrode of the second transistor. Accordingly, the second transistor is on when a logic value of "1" is stored in the gate thereof, and off when a logic value of `0` is stored in the gate thereof.

Abstract: A method for forming a metal line of a semiconductor device includes the steps of: forming an insulating film on a semiconductor substrate including a lower layer line; forming a via hole to partially expose the lower layer line by selectively removing the insulating film; forming a first conductivity material layer on the insulating film including the via hole; forming a plug layer by selectively removing the first conductivity material layer so that it remains only in the via hole; performing a resistance-lowering treatment on the plug layer to remove its impurities; and forming a second conductivity material layer on the insulating film including the plug layer to form an upper layer line.

Abstract: A metal wiring structure includes a conduction line, an insulator film for electrically insulating the conduction line, and a transmutation layer formed as the density of a portion of the insulator film adjacent to the conduction line is increased or by adding impurities to the insulator film. A metal wiring forming method for a semiconductor device, includes the step of forming a trench in a given portion of a silicon oxidation film formed on a semiconductor substrate, forming a transmutation layer on a surface of the silicon oxidation film, and depositing a conductive material on the transmutation layer to form a conduction line, whereby diffusion of the conductive material is prevented.

Abstract: A metal wire and a method for forming a metal wire of a semiconductor device, including the steps of forming an insulating layer and first etch-stop layer on a substrate forming a first trench having sidewalls and a bottom by selectively removing portions of said first etch-stop layer forming a second etch-stop layer on the insulating layer, including the first trench, and first-etch stop layer etching back said second etch-stop layer from within the trench to form a mask from said first and second etch-layers exposing a portion of the trench bottom, wherein the width of the mask has a width of less than the width of the trench bottom etching the insulating layer using said first and second etch-stop layers mask to form a second trench extending through the insulating layer for holding a contact plug removing said first and second etch-stop layers and forming a contact plug and conductive layer in said first and second trenches.

Abstract: The DRAM cell includes a first transistor, a second transistor, and a capacitor. The first and second transistors each have a gate, a source, and a drain electrode. The gate electrode of the second transistor is connected to one of the source and drain electrodes of the first transistor, and a first electrode of the capacitor is connected to the gate electrode of the second transistor. Also, a second electrode of the capacitor is connected to one of the source and drain electrodes of the second transistor. One of the source and drain electrodes of the second transistor not connected to the second electrode of the capacitor is connected to the gate electrode of the second transistor. Accordingly, the second transistor is on when a logic value of "1" is stored in the gate thereof, and off when a logic value of `0` is stored in the gate thereof.

Abstract: A programmable semiconductor element having an antifuse structure is disclosed. A first insulation film is formed on a silicon substrate. First and second conductors are formed on the first insulation film. The first and second conductors are spaced apart at a contact hole region. A second insulation film is formed on the first insulation film and the first and second conductors. The second insulation film includes a contact hole at a portion corresponding to the contact hole region. The second insulation film includes a recess adjacent to the contact hole. A conductor link is formed in the recess in the second insulation film. A third insulation film is formed over the conductor link.

Abstract: A method for the fabrication of a semiconductor device is characterized by a series of steps comprising successively forming a trench in a field region of monosilicon substrate and forming an oxidation-preventive layer and a silicon layer in the trench, and oxidizing the silicon layer into a field oxide film to produce a channel stop region beneath the trench in the substrate. The method alternatively comprises forming a trench having a small pattern in a field region of a monosilicon substrate, sequentially forming an oxidation-preventive layer and a silicon layer on the surface of the trench, and oxidizing the silicon layer and the substrate of a field region having a large pattern size, at the same time, to produce a field oxide film and channel stop diffusion regions below both the trench and the field oxide film having a large pattern.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a field oxide layer on a first conductivity-type semiconductor substrate, and forming a pattern of first active regions. The field oxide layer is selectively removed between the first active regions to pattern a second active region and word lines are formed substantially perpendicular to each of the first active regions. A second conductivity-type impurity is implanted into the substrate using a mask to form impurity diffusion regions in the first and second active regions. A first insulating layer is formed over an overall surface of the substrate, and forming a first contact hole in the second active region. A bit line is formed for contacting with the impurity diffusion region on the second active region through the first contact hole.

Abstract: A structure of an insulating layer in a semiconductor device includes a substrate, at least one inorganic insulating layer pattern formed on the substrate, and an organic insulating layer formed on an upper part of the substrate and the inorganic insulating layer pattern. Also, a method for planarizing the insulating layer includes the steps of forming a substrate, forming a base insulating layer having a step coverage to form an upper region and a lower region on the substrate, forming a first insulating layer on the base insulating layer, selectively etching the first insulating layer to form at least one first insulating layer at a lower region of the base insulating layer, and forming a second insulating layer at the upper part of the first insulating layer including a first insulating layer pattern.

Abstract: A method for forming an interconnection of a semiconductor device, includes the steps of forming an insulating layer on a substrate on which a lower conductive layer is formed, selectively removing the insulating layer to form a first connecting hole and a second connecting hole for the pattern of an upper conductive layer, growing a first conductive material in the first connecting hole to form a buried plug and then depositing a second conductive material on the surface of the insulating layer to form a barrier layer, and depositing a third conductive material on the barrier layer to fill the second connecting hole and then patterning it to form an upper conductive layer.

Abstract: Multilayered interconnection of a semiconductor device and method for forming the same, which can reduce the contact resistance and improve the reliability of a semiconductor device and is suitable for high density integration of semiconductor devices, including a substrate, an underside interconnection layer formed on the substrate, an interlayer insulation film formed on the underside interconnection layer, an upperside interconnection layer formed on the interlayer insulation film, a contact hole formed extended both in the upperside interconnection layer and the interlayer insulation film, and a plug formed in the contact hole so that the plug is in contact with the underside interconnection layer at an upper part thereof and the upperside interconnection layer at sides thereof.

Abstract: An improved semiconductor device fabrication method capable of improving the insulation characteristic between neighboring electrodes, which includes the steps of a first step which coats a conductive material on an active region of a semiconductor substrate having an active region and a non-active region divided by a field oxide film and forms a first conductive layer; a second step which deposits a first cap layer and a second cap layer in order so as to insulate between the first conductive layer and an upper layer and etches the same mask; a third step which provides ion on the semiconductor substrate with a mask of the thusly etched first conductive layer, a first cap layer, and a second cap layer and forms a source/drain region; a fourth step which forms a side wall spacer at the side surface of the first conductive layer, the first cap layer and the second cap layer and deposits in order a protection film and a contact oxide film at the front surface of the layer made thereby; a fifth step which forms

Abstract: A semiconductor memory device including a plurality of memory cells arranged in a matrix manner, each of the memory cells including a transfer transistor constituted by a gate electrode, a gate insulating film, a source region and a drain region, and a charge storage capacitor constituted by a storage node, a dielectric film and a plate electrode, the storage node of the charge storage capacitor including a cylindrical lower electrode formed above the transfer transistor via an insulating layer formed on the transfer transistor and connected to one of the source region and the drain region of the transfer transistor, and a cover type upper electrode formed on the lower electrode and connected with the lower electrode.