Abstract: An apparatus and method for forming a HSG silicon layer on a capacitor lower electrode of a semiconductor memory device. The apparatus includes a processing chamber having a plurality of source gas supply nozzles, the lengths of the nozzles being different from one another so as to uniformly supply a source gas. A loadlock chamber is placed under the processing chamber. A boat loaded with wafers is moved from the loadlock chamber to the processing chamber, with the boat being rotated while the source gas is supplied. The processing chamber and loadlock chambers are connected to a vacuum system having two vacuum pumps for maintaining a vacuum in the chambers. A third vacuum pump, connected to the processing chamber, is operated when the vacuum in the processing chamber reaches a predetermined value.

Abstract: A semiconductor wafer anchoring device, which includes a platen having a flat upper surface adapted for mounting a semiconductor wafer thereon, an elastic O-ring located between the platen and the semiconductor wafer, and a clamp disposed to face with the O-ring, which is adapted for pressing upon the upper surface of the semiconductor wafer and for anchoring same. The clamp is a ring-type plate having an inner diameter larger than the diameter of the semiconductor wafer, and having a plurality of protrusions projecting from each quadrant of an inner circumferential surface of the ring-type plate toward the center thereof, an end of each protrusion being adapted to be positioned between a chip pattern and the edge of the semiconductor wafer.

Abstract: A method of forming a hemispherical grained silicon electrode includes the steps of forming an amorphous silicon layer on an integrated circuit substrate, and heating the integrated circuit substrate and the amorphous silicon layer to a first deposition temperature. The amorphous silicon layer is exposed to a source gas including silicon while maintaining the first deposition temperature thereby forming silicon crystal nuclei on a surface of the amorphous silicon layer. The temperature of the integrated circuit substrate is lowered to a second deposition temperature wherein the second deposition temperature is less than the first deposition temperature. The silicon crystal nuclei are exposed to the source gas including silicon while maintaining the second deposition temperature thereby increasing a size of the silicon crystal nuclei.