Abstract: A touch sensing device includes a base layer, a touch electrode layer, a first reinforcing member, and a touch circuit board. The base layer includes a main area and a protruding area protruding from the main area in a first direction. The touch electrode layer is disposed on a surface of the base layer. The first reinforcing member is disposed on a surface of the protruding area. The touch circuit board is electrically connected to the touch electrode layer. The protruding area includes a bending area and a pad area. The bending area is bent downward. The pad area extends from the bending area in the first direction and overlaps the base layer in a second direction intersecting the first direction in a bent state of the bending area. The touch circuit board is attached to the pad area.

Abstract: Integrated circuit (IC) structures, electronic modules, and methods of fabrication are described in which direct bonded interfaces are removed at corners or edges to counteract the potential for non-bonding or delamination. This can be accomplished during singulation, in which a side recess is formed through an entire thickness of an electronic component and into a direct bonded die, followed by final singulation of the IC structure.

Abstract: Provided herein may be an electronic device and a method of operating the same. The electronic device may include a memory device, and a controller configured to receive an inbound protocol information unit (PIU) from an external device and control the memory device based on the inbound PIU, wherein the inbound PIU includes a basic header segment including information about an extra header segment (EHS) length, and an extra header segment defined by the EHS length, and wherein the controller is configured to generate an error message depending on whether the PIU includes an error related to the extra header segment.

Abstract: Microelectronic structures with selectively applied underfill material and/or edge bond material are described. In an embodiment, isolated underfill regions and/or edge bond regions are applied to adjacent to one or more edges of an electronic device and form a plurality of vent openings along the one or more edges.

Abstract: According to an embodiment of the present disclosure, a storage device may include a memory device, and a memory controller configured to receive a read command from an external host and control the memory device according to the read command, wherein the read command may include a basic header segment commonly included in commands transferred between the external host and the memory controller and including information indicating that the read command is a command for requesting data stored in the memory device, a transaction specific field including information indicating that the read command is a read command for at least two or more logical addresses, and an extra header segment including information on the at least two or more logical addresses.

Abstract: According to an embodiment of the present disclosure, a storage device may include a memory device, and a memory controller configured to receive a read command from an external host and control the memory device according to the read command, wherein the read command may include a basic header segment commonly included in commands transferred between the external host and the memory controller and including information indicating that the read command is a command for requesting data stored in the memory device, a transaction specific field including information indicating that the read command is a read command for at least two or more logical addresses, and an extra header segment including information on the at least two or more logical addresses.

Abstract: A data processing system may include: a memory system including an error history region, the memory system suitable for storing in the error history region, error history data related to an internal error, and a host suitable for obtaining the error history data from the memory system by providing the memory system with an error history read command, performing failure analysis of the memory system on the basis of the obtained error history data, and controlling the memory system to clear at least a portion of the error history region by providing the memory system with an error history clear command, wherein the error history region is a memory region that is not able to be accessed with a logical address used by the host.

Abstract: A memory controller to control a memory device including a secure storage area may include a host interface configured to receive a command from a host, the command including information for authentication requesting access to the secure storage area; a processor configured to generate a device authentication code based on the information for the authentication; and a memory interface configured to access the secure storage area under control of the processor, and the processor may perform at least a portion of an operation of the device authentication code while the host interface or the memory interface receives data, following the command.

Abstract: According to an embodiment of the present technology, a storage device may include a memory device including a secure storage area for storing therein data to be accessed according to authentication; an access mode memory configured to store therein information of device access mode regarding an operation mode for the secure storage area; and a memory controller configured to receive a command regarding the secure storage area from an external host and process the command according to whether information of host access mode included in the command matches the information of the device access mode.

Abstract: According to an embodiment of the present disclosure, a storage device may include a memory device, and a memory controller configured to receive a read command from an external host and control the memory device according to the read command, wherein the read command may include a basic header segment commonly included in commands transferred between the external host and the memory controller and including information indicating that the read command is a command for requesting data stored in the memory device, a transaction specific field including information indicating that the read command is a read command for at least two or more logical addresses, and an extra header segment including information on the at least two or more logical addresses.

Abstract: A data processing system may include: a memory system including an error history region, the memory system suitable for storing in the error history region, error history data related to an internal error, and a host suitable for obtaining the error history data from the memory system by providing the memory system with an error history read command, performing failure analysis of the memory system on the basis of the obtained error history data, and controlling the memory system to clear at least a portion of the error history region by providing the memory system with an error history clear command, wherein the error history region is a memory region that is not able to be accessed with a logical address used by the host.