Patents by Inventor Young Kyu JEON
Young Kyu JEON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12289844Abstract: A display device includes a cover module having a storage space therein, a display panel configured to be at least partially disposed inside the storage space or withdrawn outside the storage space, and a first driving system configured to embed the display panel into the cover module or withdraw the display panel from the cover module in a first direction, wherein the first driving system includes a first rigid chain.Type: GrantFiled: December 19, 2022Date of Patent: April 29, 2025Assignee: LG Display Co., Ltd.Inventors: Eun-Gi Jeon, Young-Kyu Bang, Sung-Hwan Yoon, Seoung-Mo Kang
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Patent number: 12279384Abstract: A display device includes a cover module having a storage space therein, a display panel configured to be at least partially disposed inside the storage space or withdrawn outside the storage space, and a first driving system configured to embed and withdraw the display panel into and from the cover module in a first direction, wherein the first driving system includes a first wire drum and a first driving wire.Type: GrantFiled: December 3, 2022Date of Patent: April 15, 2025Assignee: LG Display Co., Ltd.Inventors: Sung-Hwan Yoon, Young-Kyu Bang, Seoung-Mo Kang, Eun-Gi Jeon
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Publication number: 20250050336Abstract: A pattern electrode structure for an electrowetting device is laminated between a base material and a dielectric layer of the electrowetting device, and the pattern electrode structure includes first branch electrodes formed in a direction perpendicular to any plane perpendicular to a plane defined by the pattern electrode structure, and a basal pattern electrode formed in an area below lower ends of the first branch electrodes and connected to an electrode connection portion configured to receive a voltage, in which a sum of an interval between the first branch electrode and the basal pattern electrode and a width of the basal pattern electrode is larger than a diameter of a droplet to be removed, thereby preventing the droplet from stagnating without falling at the terminal end of the pattern in a structure that uses the vertical pattern.Type: ApplicationFiled: October 19, 2023Publication date: February 13, 2025Inventors: Kwang-Joon Han, Yu-Bin Jeon, Byung-Kyu Cho, Sung-Hun Han, Hong-Jun Cha, Young-Ern Jung
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Publication number: 20250053000Abstract: An embodiment pattern electrode structure for an electrowetting device includes a first branch electrode disposed in a direction perpendicular to any plane that is perpendicular to a plane defined by the pattern electrode structure and a basal pattern electrode disposed in an area above an upper end of the first branch electrode and connected to an electrode connection portion configured to receive a voltage, wherein an interval between the first branch electrode and the basal pattern electrode is equal to or larger than a diameter of a droplet to be removed.Type: ApplicationFiled: November 8, 2023Publication date: February 13, 2025Inventors: Kwang-Joon Han, Yu-Bin Jeon, Byung-Kyu Cho, Sung-Hun Han, Hong-Jun Cha, Young-Ern Jung
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Publication number: 20240329877Abstract: Provided herein may be an electronic device and a method of operating the same. The electronic device may include a memory device, and a controller configured to receive an inbound protocol information unit (PIU) from an external device and control the memory device based on the inbound PIU, wherein the inbound PIU includes a basic header segment including information about an extra header segment (EHS) length, and an extra header segment defined by the EHS length, and wherein the controller is configured to generate an error message depending on whether the PIU includes an error related to the extra header segment.Type: ApplicationFiled: October 5, 2023Publication date: October 3, 2024Inventors: Byung Jun KIM, Ji Wook KIM, Young Woo LEE, Won Kyoo LEE, Taek Gyu LEE, Young Kyu JEON, Kyoung Ku CHO
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Publication number: 20240037023Abstract: According to an embodiment of the present disclosure, a storage device may include a memory device, and a memory controller configured to receive a read command from an external host and control the memory device according to the read command, wherein the read command may include a basic header segment commonly included in commands transferred between the external host and the memory controller and including information indicating that the read command is a command for requesting data stored in the memory device, a transaction specific field including information indicating that the read command is a read command for at least two or more logical addresses, and an extra header segment including information on the at least two or more logical addresses.Type: ApplicationFiled: October 13, 2023Publication date: February 1, 2024Inventors: Byung Jun KIM, Jea Young ZHANG, Young Kyu JEON, Kyoung Ku CHO
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Patent number: 11815938Abstract: According to an embodiment of the present disclosure, a storage device may include a memory device, and a memory controller configured to receive a read command from an external host and control the memory device according to the read command, wherein the read command may include a basic header segment commonly included in commands transferred between the external host and the memory controller and including information indicating that the read command is a command for requesting data stored in the memory device, a transaction specific field including information indicating that the read command is a read command for at least two or more logical addresses, and an extra header segment including information on the at least two or more logical addresses.Type: GrantFiled: June 14, 2022Date of Patent: November 14, 2023Assignee: SK hynix Inc.Inventors: Byung Jun Kim, Jea Young Zhang, Young Kyu Jeon, Kyoung Ku Cho
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Patent number: 11782782Abstract: A data processing system may include: a memory system including an error history region, the memory system suitable for storing in the error history region, error history data related to an internal error, and a host suitable for obtaining the error history data from the memory system by providing the memory system with an error history read command, performing failure analysis of the memory system on the basis of the obtained error history data, and controlling the memory system to clear at least a portion of the error history region by providing the memory system with an error history clear command, wherein the error history region is a memory region that is not able to be accessed with a logical address used by the host.Type: GrantFiled: December 17, 2021Date of Patent: October 10, 2023Assignee: SK hynix Inc.Inventors: Seung Hun Kim, Young Kyu Jeon
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Publication number: 20230134534Abstract: A memory controller to control a memory device including a secure storage area may include a host interface configured to receive a command from a host, the command including information for authentication requesting access to the secure storage area; a processor configured to generate a device authentication code based on the information for the authentication; and a memory interface configured to access the secure storage area under control of the processor, and the processor may perform at least a portion of an operation of the device authentication code while the host interface or the memory interface receives data, following the command.Type: ApplicationFiled: November 3, 2022Publication date: May 4, 2023Inventors: Hui Won LEE, Byung Jun KIM, Taek Gyu LEE, Young Kyu JEON
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Publication number: 20230136229Abstract: According to an embodiment of the present technology, a storage device may include a memory device including a secure storage area for storing therein data to be accessed according to authentication; an access mode memory configured to store therein information of device access mode regarding an operation mode for the secure storage area; and a memory controller configured to receive a command regarding the secure storage area from an external host and process the command according to whether information of host access mode included in the command matches the information of the device access mode.Type: ApplicationFiled: September 12, 2022Publication date: May 4, 2023Inventors: Hui Won LEE, Byung Jun KIM, Taek Gyu LEE, Young Kyu JEON
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Publication number: 20230026323Abstract: According to an embodiment of the present disclosure, a storage device may include a memory device, and a memory controller configured to receive a read command from an external host and control the memory device according to the read command, wherein the read command may include a basic header segment commonly included in commands transferred between the external host and the memory controller and including information indicating that the read command is a command for requesting data stored in the memory device, a transaction specific field including information indicating that the read command is a read command for at least two or more logical addresses, and an extra header segment including information on the at least two or more logical addresses.Type: ApplicationFiled: June 14, 2022Publication date: January 26, 2023Inventors: Byung Jun KIM, Jea Young Zhang, Young Kyu Jeon, Kyoung Ku Cho
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Publication number: 20220334905Abstract: A data processing system may include: a memory system including an error history region, the memory system suitable for storing in the error history region, error history data related to an internal error, and a host suitable for obtaining the error history data from the memory system by providing the memory system with an error history read command, performing failure analysis of the memory system on the basis of the obtained error history data, and controlling the memory system to clear at least a portion of the error history region by providing the memory system with an error history clear command, wherein the error history region is a memory region that is not able to be accessed with a logical address used by the host.Type: ApplicationFiled: December 17, 2021Publication date: October 20, 2022Inventors: Seung Hun KIM, Young Kyu JEON