Patents by Inventor Young Kyu JEON

Young Kyu JEON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240037023
    Abstract: According to an embodiment of the present disclosure, a storage device may include a memory device, and a memory controller configured to receive a read command from an external host and control the memory device according to the read command, wherein the read command may include a basic header segment commonly included in commands transferred between the external host and the memory controller and including information indicating that the read command is a command for requesting data stored in the memory device, a transaction specific field including information indicating that the read command is a read command for at least two or more logical addresses, and an extra header segment including information on the at least two or more logical addresses.
    Type: Application
    Filed: October 13, 2023
    Publication date: February 1, 2024
    Inventors: Byung Jun KIM, Jea Young ZHANG, Young Kyu JEON, Kyoung Ku CHO
  • Patent number: 11815938
    Abstract: According to an embodiment of the present disclosure, a storage device may include a memory device, and a memory controller configured to receive a read command from an external host and control the memory device according to the read command, wherein the read command may include a basic header segment commonly included in commands transferred between the external host and the memory controller and including information indicating that the read command is a command for requesting data stored in the memory device, a transaction specific field including information indicating that the read command is a read command for at least two or more logical addresses, and an extra header segment including information on the at least two or more logical addresses.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: November 14, 2023
    Assignee: SK hynix Inc.
    Inventors: Byung Jun Kim, Jea Young Zhang, Young Kyu Jeon, Kyoung Ku Cho
  • Patent number: 11782782
    Abstract: A data processing system may include: a memory system including an error history region, the memory system suitable for storing in the error history region, error history data related to an internal error, and a host suitable for obtaining the error history data from the memory system by providing the memory system with an error history read command, performing failure analysis of the memory system on the basis of the obtained error history data, and controlling the memory system to clear at least a portion of the error history region by providing the memory system with an error history clear command, wherein the error history region is a memory region that is not able to be accessed with a logical address used by the host.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: October 10, 2023
    Assignee: SK hynix Inc.
    Inventors: Seung Hun Kim, Young Kyu Jeon
  • Publication number: 20230136229
    Abstract: According to an embodiment of the present technology, a storage device may include a memory device including a secure storage area for storing therein data to be accessed according to authentication; an access mode memory configured to store therein information of device access mode regarding an operation mode for the secure storage area; and a memory controller configured to receive a command regarding the secure storage area from an external host and process the command according to whether information of host access mode included in the command matches the information of the device access mode.
    Type: Application
    Filed: September 12, 2022
    Publication date: May 4, 2023
    Inventors: Hui Won LEE, Byung Jun KIM, Taek Gyu LEE, Young Kyu JEON
  • Publication number: 20230134534
    Abstract: A memory controller to control a memory device including a secure storage area may include a host interface configured to receive a command from a host, the command including information for authentication requesting access to the secure storage area; a processor configured to generate a device authentication code based on the information for the authentication; and a memory interface configured to access the secure storage area under control of the processor, and the processor may perform at least a portion of an operation of the device authentication code while the host interface or the memory interface receives data, following the command.
    Type: Application
    Filed: November 3, 2022
    Publication date: May 4, 2023
    Inventors: Hui Won LEE, Byung Jun KIM, Taek Gyu LEE, Young Kyu JEON
  • Publication number: 20230026323
    Abstract: According to an embodiment of the present disclosure, a storage device may include a memory device, and a memory controller configured to receive a read command from an external host and control the memory device according to the read command, wherein the read command may include a basic header segment commonly included in commands transferred between the external host and the memory controller and including information indicating that the read command is a command for requesting data stored in the memory device, a transaction specific field including information indicating that the read command is a read command for at least two or more logical addresses, and an extra header segment including information on the at least two or more logical addresses.
    Type: Application
    Filed: June 14, 2022
    Publication date: January 26, 2023
    Inventors: Byung Jun KIM, Jea Young Zhang, Young Kyu Jeon, Kyoung Ku Cho
  • Publication number: 20220334905
    Abstract: A data processing system may include: a memory system including an error history region, the memory system suitable for storing in the error history region, error history data related to an internal error, and a host suitable for obtaining the error history data from the memory system by providing the memory system with an error history read command, performing failure analysis of the memory system on the basis of the obtained error history data, and controlling the memory system to clear at least a portion of the error history region by providing the memory system with an error history clear command, wherein the error history region is a memory region that is not able to be accessed with a logical address used by the host.
    Type: Application
    Filed: December 17, 2021
    Publication date: October 20, 2022
    Inventors: Seung Hun KIM, Young Kyu JEON