Abstract: The disclosure relates to a wireless communication system, in which a method performed by a user equipment includes receiving, from a base station, information configuring a plurality of sounding reference signal (SRS) resources that are related with one channel state information-reference signal (CSI-RS) resource, receiving an SRS resource indicator (SRI) indicating at least one SRS resource from among the plurality of SRS resources, obtaining, based on an implicit precoding being indicated for an uplink channel, precoding information for the uplink channel based on the CSI-RS resource related with a most recently transmitted SRS of the at least one SRS resource indicated by the SRI, and transmitting, to the base station, the uplink channel based on the precoding information.

Abstract: A semiconductor device includes: a fuse set unit including a plurality of fuse sets, each fuse set including one or more address fuses and an enable fuse; a rupture control unit suitable for controlling the enable fuse of a selected fuse set to be programmed after the address fuses of the selected fuse set is programmed, during a program operation; a cell data verify unit suitable for repeatedly performing a verify and rupture operation on the selected fuse set during the program operation, determining whether read data from the selected fuse set is identical to target data corresponding to a rupture address through a final verify operation, and outputting fail information; and a fuse set control unit suitable for controlling the program operation to be performed on a different fuse set after the program operation on the selected fuse set is terminated, in response to the fail information.

Abstract: A semiconductor device includes a fuse selection circuit suitable for generating fuse set address signals based on a clock signal; a fuse array including a plurality of fuse sets and suitable for sequentially outputting fuse set data from the fuse sets based on the fuse set address signals; a read circuit suitable for sequentially generating read set data based on the clock signal and the fuse set data; and a calculation circuit suitable for calculating a number of used or unused fuse sets among the fuse sets based on the clock signal and a fuse information signal which includes at least one fuse read signal among a plurality of fuse read signals included in the read set data.

Abstract: A semiconductor device includes a fuse selection circuit suitable for generating fuse set address signals based on a clock signal; a fuse array including a plurality of fuse sets and suitable for sequentially outputting fuse set data from the fuse sets based on the fuse set address signals; a read circuit suitable for sequentially generating read set data based on the clock signal and the fuse set data; and a calculation circuit suitable for calculating a number of used or unused fuse sets among the fuse sets based on the clock signal and a fuse information signal which includes at least one fuse read signal among a plurality of fuse read signals included in the read set data.

Abstract: A semiconductor device includes: a fuse set unit including a plurality of fuse sets, each fuse set including one or more address fuses and an enable fuse; a rupture control unit suitable for controlling the enable fuse of a selected fuse set to be programmed after the address fuses of the selected fuse set is programmed, during a program operation; a cell data verify unit suitable for repeatedly performing a verify and rupture operation on the selected fuse set during the program operation, determining whether read data from the selected fuse set is identical to target data corresponding to a rupture address through a final verify operation, and outputting fail information; and a fuse set control unit suitable for controlling the program operation to be performed on a different fuse set after the program operation on the selected fuse set is terminated, in response to the fail information.

Abstract: A post package repair (PPR) device is disclosed, which relates to a technology for masking a rupture operation in case of a post package repair (PPR) operation. The post package repair (PPR) device includes: a plurality of bank groups, each including a fuse indicating repair information, configured to share a predetermined number of fuses; a resource detection unit configured to generate a resource signal which determines whether the fuses from among the plurality of bank groups are available; and a masking controller configured to output a masking signal which prevents repeated execution of a rupture operation when there is no unused fuse in response to the resource signal and a bank active signal.

Abstract: A semiconductor device includes a latch circuit suitable for storing a test result; a non-volatile memory circuit suitable for storing information used for an operation of the semiconductor device; a decoding unit suitable for generating one or more internal program commands by using one or more control signals; and a control unit suitable for programming information in the non-volatile memory circuit in response to the test result stored in the latch circuit when the internal program commands are activated.

Abstract: A semiconductor system includes a controller configured to generate a boot-up signal; and a semiconductor device configured to, if addresses, which increase by a predetermined value, have the same combination of bits as fuse data, initialize fuse data in response to the boot-up signal or a reset signal, and generate the fuse data by using latched internal fuse data after the fuse data are initialized.

Abstract: A post package repair (PPR) device is disclosed, which relates to a technology for masking a rupture operation in case of a post package repair (PPR) operation. The post package repair (PPR) device includes: a plurality of bank groups, each including a fuse indicating repair information, configured to share a predetermined number of fuses; a resource detection unit configured to generate a resource signal which determines whether the fuses from among the plurality of bank groups are available; and a masking controller configured to output a masking signal which prevents repeated execution of a rupture operation when there is no unused fuse in response to the resource signal and a bank active signal.

Abstract: A post package repair device may include a plurality of bank groups, each of the plurality of bank groups including fuses indicating repair information, configured to share a predetermined number of fuses. The post package repair device may include a resource detection unit configured to determine the availability of the fuses from among the plurality of bank groups.

Abstract: A post package repair device may include a plurality of bank groups, each of the plurality of bank groups including fuses indicating repair information, configured to share a predetermined number of fuses. The post package repair device may include a resource detection unit configured to determine the availability of the fuses from among the plurality of bank groups.

Abstract: A memory device includes a memory array, a test circuit suitable for detecting a first repair address corresponding to a defective cell in the memory array, in a test mode, an external input circuit suitable for receiving a second repair address from an exterior, in response to an address input command, in an external input mode, and a nonvolatile memory circuit suitable for programming the first repair address in a first region in response to a first program command in the test mode, and programming the second repair address in a second region in response to a second program command in the external input mode, wherein the first repair address is programmed in the second region in response to the second program command while the address input command is deactivated in the external input mode.

Abstract: A semiconductor device includes a latch circuit suitable for storing a test result; a non-volatile memory circuit suitable for staring information used for an operation of the semiconductor device; a decoding unit suitable for generating one or more internal program commands by using one or more control signals; and a control unit suitable for programming information in the non-volatile memory circuit in response to the test result stored in the latch circuit when the internal program commands are activated.

Abstract: A memory device includes a memory array, a test circuit suitable for detecting a first repair address corresponding to a defective cell in the memory array, in a test mode, an external input circuit suitable for receiving a second repair address from an exterior, in response to an address input command, in an external input mode, and a nonvolatile memory circuit suitable for programming the first repair address in a first region in response to a first program command in the test mode, and programming the second repair address in a second region in response to a second program command in the external input mode, wherein the first repair address is programmed in the second region in response to the second program command while the address input command is deactivated in the external input mode.

Abstract: A precharge signal generation circuit includes a control signal generation unit configured to activate a control signal in response to a read command or write command and a precharge signal generation unit configured to use a clock signal in a period when the control signal is activated to activate a precharge signal at a time point when a delay time passes from an input of the read command or the write command to precharge signal generation circuit.

Abstract: A signal transfer circuit includes a signal transfer unit configured to transfer an input signal applied to an input node to an output node in response to a control signal and a driving unit configured to drive an output signal of the output node to a level of the input signal in response to the control signal.

Abstract: A semiconductor memory apparatus may comprise: an input buffer block configured to receive a write signal and a reference level signal, compare a the write signal with a the reference level signal to generate a first write control signal, and delay the first write control signal by a predetermined time to generate a second write control signal; a first decoder block configured to combine the second write control signal inputted from the input buffer block with externally inputted command signals, and generate a first write command signal; a clock control block configured to generate a clock control signal for determining determine a level of an internal clock signal in response to a level of the first write control signal outputted from the input buffer block; and a write signal control block configured to generate an internal write command signal according to a level of the first write command signal inputted from the first decoder block and the clock control signal inputted from the clock control block.

Abstract: A precharge signal generation circuit includes a control signal generation unit configured to activate a control signal in response to a read command or write command and a precharge signal generation unit configured to use a clock signal in a period when the control signal is activated to activate a precharge signal at a time point when a delay time passes from an input of the read command or the write command to precharge signal generation circuit.

Abstract: A signal transfer circuit includes a signal transfer unit configured to transfer an input signal applied to an input node to an output node in response to a control signal and a driving unit configured to drive an output signal of the output node to a level of the input signal in response to the control signal.

Abstract: A semiconductor memory apparatus may comprise: an input buffer block configured to receive a write signal and a reference level signal, compare a the write signal with a the reference level signal to generate a first write control signal, and delay the first write control signal by a predetermined time to generate a second write control signal; a first decoder block configured to combine the second write control signal inputted from the input buffer block with externally inputted command signals, and generate a first write command signal; a clock control block configured to generate a clock control signal for determining determine a level of an internal clock signal in response to a level of the first write control signal outputted from the input buffer block; and a write signal control block configured to generate an internal write command signal according to a level of the first write command signal inputted from the first decoder block and the clock control signal inputted from the clock control block.