Abstract: A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

Abstract: The present invention relates to a method for producing tagatose using soy oligosaccharide or soluble sugar solution containing the same, more precisely, a method for producing tagatose comprising the following steps; hydrolyzing soy oligosaccharide by using ?-galactosidase selectively; producing tagatose continuously by enzymatic isomerization of galactose obtained from the hydrolysate; separating the produced tagatose by chromatography; and recycling the non-reacted materials.

Abstract: The present invention relates to a cascade enzyme-linked immunosorbent assay, more precisely a cascade enzyme-linked immunosorbent assay using magnetic microparticles (MMPs) immobilized with the target antigen specific primary antibody and silica nanoparticles (SPs) immobilized with a cascade reaction initiator and the antigen-specific secondary antibody. When the method of the present invention is applied in the detection of an antigen in biosamples, the detection sensitivity can be significantly increased.

Abstract: A method of fabricating a semiconductor device including a fin field effect transistor (Fin-FET) includes forming sacrificial bars on a semiconductor substrate, patterning the sacrificial bars to form sacrificial islands on the semiconductor substrate, forming a device isolation layer to fill a space between the sacrificial islands, selectively removing the sacrificial islands to expose the semiconductor substrate below the sacrificial islands, and anisotropically etching the exposed semiconductor substrate using the device isolation layer as an etch mask to form a recessed channel region. The recessed channel region allows the channel width and channel length of a transistor to be increased, thereby reducing the occurrence of short channel effects and narrow channel effects in highly integrated semiconductor devices.

Abstract: A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

Abstract: A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

Abstract: The present invention relates to a recombinant GRAS (Generally Recognized As Safe) strains expressing thermophilic arabinose isomerase as an active form and method of food grade tagatose by using the same, and more precisely, a gene encoding arabinose isomerase originating from the thermophilic Geobacillus stearothermophilus DSM22 and Geobacillus thermodenitrificans, a recombinant expression vector containing the gene, a recombinant GRAS strains expressing the thermophilic arabinose isomerase as an active form by transformed with the expression vector, and a method of preparing food grade tagatose from galactose by using the same.

Abstract: The present invention relates to a thermophilic arabinose isomerase and a method of manufacturing tagatose using the same, and more precisely, a gene encoding arabinose isomerase originating from the thermophile Thermotoga neapolitana DSM 5068, a recombinant expression vector containing the gene, a method of preparing a food grade thermophilic arabinose isomerase from the recombinant GRAS (Generally Recognized As Safe) strain transformed with the said expression vector, and a method of preparing tagatose from galactose using the said enzyme.

Abstract: A printed circuit board is disclosed. The printed circuit board, which may include an insulation layer, a first metal pad formed on the insulation layer, a second metal pad electrically coupled with the first metal pad and having an ionization tendency lower than that of the first metal pad, and a sacrificial electrode electrically coupled with the second metal pad to prevent corrosion in the first metal pad, can be utilized to prevent excessive etching that may otherwise occur due to galvanic corrosion between metal pads of different ionization tendencies.

Abstract: A method of manufacturing a mask includes designing a second mask data pattern for forming a first mask data pattern, creating a first emulation pattern, which is determined from the second mask data pattern, using a first emulation, creating a second emulation pattern, which is determined from the first emulation pattern, using a second emulation, comparing a pattern, in which the first and second emulation patterns overlap, with the first mask data pattern, and manufacturing a mask layer, which corresponds to the second mask data pattern, according to results of the comparison.

Abstract: In a thin layer structure and a method of forming the same, a first preliminary insulation pattern is formed on a substrate and includes a first opening exposing the substrate. One or more preliminary seed patterns including single crystalline silicon are formed in the first opening. A second insulation layer is formed on the first preliminary insulation pattern and the one or more preliminary seed patterns. A second insulation pattern, a first insulation pattern and one or more seed patterns are formed by etching the first and second insulation layers and the one or more preliminary seed patterns. The second insulation pattern includes a second opening having a flat bottom portion. A single crystalline silicon pattern is formed in the second opening, wherein a central thickness of the single crystalline silicon pattern is substantially identical to a peripheral thickness thereof, thereby reducing or preventing a thinning defect in a semiconductor device.

Abstract: A method of forming an ion implantation mask includes forming a field area on a semiconductor substrate, forming an amorphous carbon layer on the semiconductor substrate, forming a hard mask layer on the amorphous carbon layer, forming an etching mask pattern on the hard mask layer, and etching the hard mask layer and the amorphous carbon layer to expose the field area through the etching mask pattern, wherein etching the hard mask layer and the amorphous carbon layer forms a hard mask layer pattern and an amorphous carbon layer pattern.

Abstract: A printed circuit board is disclosed. The printed circuit board, which has at least one pad on which a solder ball is to be placed, includes a solder resist that covers a surface of the printed circuit board, an opening part that exposes the pad and supports the solder ball, and an extended portion formed in a perimeter of the opening part that allows an underfill to flow in between the printed circuit board and the solder ball. With this printed circuit board, the underfill can be filled in more readily between the printed circuit board and the solder balls, when mounting a component on the printed circuit board.

Abstract: A new concept card and a selling system and method based on a purchaser using the card are disclosed. The system includes a card system 4 which issues a new concept card for allowing a card company to identify a seller or registers or grants information to a seller, a seller system 3 or terminal 31 which allows the seller to receive the UC or information and to advertise the card or information to a purchaser and allows the purchaser to purchase merchandise, a purchaser terminal 1 which allows the purchaser to access the seller system or terminal so as to purchase merchandise or acquire the UC information and to access the card company to rapidly/accurately input the UC or seller information such that credit card approval is requested, and a bank system 2 which processes the credit car approval when the purchaser requests the credit card approval.

Abstract: A protein biosensor having increased signal intensity to sugar concentration and the use thereof. A fluorescent indicator protein is described, in which fluorescent proteins of different emission ranges are fused to both ends of a binding protein undergoing a conformational change due to binding of sugars, such that a change in the concentration of various sugars involved in intracellular metabolism, e.g., maltose, can be detected by measuring a change in emission intensities, caused by FRET (fluorescence resonance energy transfer). A method for detecting a change in the concentration of sugars using such fluorescent indicator protein is also described. The fluorescent indicator protein has excellent signal intensity enabling precision measurement of intracellular concentration of various sugars. In one implementation, high signal intensity fluorescent indicator proteins can be prepared from proteins otherwise used as biosensors, to enable them to be more widely useful.

Abstract: The present invention relates to a thermophilic arabinose isomerase and a method of manufacturing tagatose using the same, and more precisely, a gene encoding arabinose isomerase originating from the thermophilic Thermotoga neapolitana DSM 5068, a recombinant expression vector containing the gene, a method of preparing a food grade thermophilic arabinose isomerase from the recombinant GRAS (Generally Recognized As Safe) strain transformed with the said expression vector, and a method of preparing tagatose from galactose using the said enzyme.

Abstract: The present invention relates to a thermophilic arabinose isomerase and a method of manufacturing tagatose using the same, and more precisely, a gene encoding arabinose isomerase originating from the thermophile Geobacillus stearothermophilus DSM22, a recombinant expression vector containing the gene, a method of preparing a food grade thermophilic arabinose isomerase from the recombinant GRAS (Generally Recognized As Safe) strain transformed with the said expression vector, and a method of preparing tagatose from galactose using the said enzyme.

Abstract: A method of fabricating a semiconductor device including a fin field effect transistor (Fin-FET) includes forming sacrificial bars on a semiconductor substrate, patterning the sacrificial bars to form sacrificial islands on the semiconductor substrate, forming a device isolation layer to fill a space between the sacrificial islands, selectively removing the sacrificial islands to expose the semiconductor substrate below the sacrificial islands, and anisotropically etching the exposed semiconductor substrate using the device isolation layer as an etch mask to form a recessed channel region. The recessed channel region allows the channel width and channel length of a transistor to be increased, thereby reducing the occurrence of short channel effects and narrow channel effects in highly integrated semiconductor devices.

Abstract: A method of manufacturing a mask includes designing a second mask data pattern for forming a first mask data pattern, creating a first emulation pattern, which is determined from the second mask data pattern, using a first emulation, creating a second emulation pattern, which is determined from the first emulation pattern, using a second emulation, comparing a pattern, in which the first and second emulation patterns overlap, with the first mask data pattern, and manufacturing a mask layer, which corresponds to the second mask data pattern, according to results of the comparison.

Abstract: A method and mask having balance patterns for reducing and/or preventing chemical flare from occurring in a photoresist between a first mask region and a second mask region. Balance patterns formed on the mask may have a desired and/or predetermined pitch and may be regularly arranged. If the pitch of the balance patterns is equal to or smaller than a threshold value, the balance patterns may not allow the patterns to be transferred onto a photoresist. In addition, the photoresist corresponding to the balance patterns may be either completely removed or completely remain depending on the duty of the balance patterns.