Abstract: A conductive composite material, a method of preparing the same, and a secondary battery including the same. The conductive composite material may increase the proportion of an active material when forming an electrode by chemically bonding a conductive material and a binder to each other. A method of preparing the conductive composite material comprises ionizing carbon-based particles in a predetermined polarity, ionizing PTFE particles in a polarity different from that of the carbon-based particles, and chemically bonding the ionized carbon-based particles and the ionized PTFE particles, which are ionized in different polarities, to each other.

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip, wherein the first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pad, the semiconductor chip includes a passivation layer having an opening exposing at least a portion of the connection pad, the redistribution layer of the second interconnection member is connected to the connection pad through a via, and the via covers at least a portion of the passivation layer.

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip, wherein the first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pad, the semiconductor chip includes a passivation layer having an opening exposing at least a portion of the connection pad, the redistribution layer of the second interconnection member is connected to the connection pad through a via, and the via covers at least a portion of the passivation layer.

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip, wherein the first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pad, the semiconductor chip includes a passivation layer having an opening exposing at least a portion of the connection pad, the redistribution layer of the second interconnection member is connected to the connection pad through a via, and the via covers at least a portion of the passivation layer.

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip, wherein the first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pad, the semiconductor chip includes a passivation layer having an opening exposing at least a portion of the connection pad, the redistribution layer of the second interconnection member is connected to the connection pad through a via, and the via covers at least a portion of the passivation layer.

Abstract: An EMI noise reduction package board, having a top layer and a bottom layer, one of which having a semiconductor device mounted thereon, can include: a first area having a signal layer arranged on one surface thereof; and a second area placed on a lateral side of the first area and having unit structures arranged repeatedly therein, the unit structures configured for inhibiting EMI noise from being radiated to an outside through the lateral side of the first area. The unit structure can include: a top conductive plate and a bottom conductive plate, formed, respectively, on the top layer and the bottom layer of the second area to face each other in a pair; and a via, connecting the top conductive plate with the bottom conductive plate.

Abstract: An EMI noise reduction package board, having a top layer and a bottom layer, one of which having a semiconductor device mounted thereon, can include: a first area having a signal layer arranged on one surface thereof; and a second area placed on a lateral side of the first area and having unit structures arranged repeatedly therein, the unit structures configured for inhibiting EMI noise from being radiated to an outside through the lateral side of the first area. The unit structure can include: a top conductive plate and a bottom conductive plate, formed, respectively, on the top layer and the bottom layer of the second area to face each other in a pair; and a via, connecting the top conductive plate with the bottom conductive plate.