Patents by Inventor Young-Min Kwon

Young-Min Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030042539
    Abstract: A method of forming a shallow trench isolation type semiconductor device comprises forming an etch protecting layer pattern to define at least one active region on a substrate, forming at least one trench by etching the substrate partially by using the etch protecting layer pattern as an etch mask, forming a thermal-oxide film on an inner wall of the trench, filling the trench having the thermal-oxide film with a CVD silicon oxide layer to form an isolation layer, removing the etch protecting layer pattern from the substrate over which the isolation layer is formed, removing the thermal-oxide film formed on a top end of the inner wall of the trench to a depth of 100 to 350 Å, preferably 200 Å from the upper surface of the substrate, and forming a gate oxide film on the substrate from which the active region and the top end are exposed.
    Type: Application
    Filed: October 21, 2002
    Publication date: March 6, 2003
    Applicant: SAMSUNG ELECTRONICS CO., LTD
    Inventors: Keum-Joo Lee, Young-Min Kwon, Chang-Lyoung Song, In-Seak Hwang
  • Patent number: 6513538
    Abstract: A method for removing contaminants from an integrated circuit substrate include treating the substrate with a hydrogen peroxide cleaning solution containing a chelating agent, and treating the substrate with hydrogen gas and fluorine-containing gas, and annealing the substrate. Cleaning solutions includes ammonium, hydrogen peroxide, deionized water, and chelating agent. The chelating agent includes one to three compounds selected from the group consisting of carboxylic acid compounds, phosphonic acid compounds, and hydroxyl aromatic compounds. The fluorine-containing gas is a gas selected from the group consisting of nitrogen trifluoride (NF3), hexafluorosulphur (SF6), and trifluorochlorine (ClF3).
    Type: Grant
    Filed: May 22, 2001
    Date of Patent: February 4, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-pil Chung, Kyu-hwan Chang, Young-min Kwon, Sang-lock Hah
  • Patent number: 6500726
    Abstract: A method of forming a shallow trench isolation type semiconductor device comprises forming an etch protecting layer pattern to define at least one active region on a substrate, forming at least one trench by etching the substrate partially by using the etch protecting layer pattern as an etch mask, forming a thermal-oxide film on an inner wall of the trench, filling the trench having the thermal-oxide film with a CVD silicon oxide layer to form an isolation layer, removing the etch protecting layer pattern from the substrate over which the isolation layer is formed, removing the thermal-oxide film formed on a top end of the inner wall of the trench to a depth of 100 to 350 Å, preferably 200 Å from the upper surface of the substrate, and forming a gate oxide film on the substrate from which the active region and the top end are exposed.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: December 31, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keum-Joo Lee, Young-Min Kwon, Chang-Lyoung Song, In-Seak Hwang
  • Publication number: 20020195125
    Abstract: A wafer drying method includes submerging a wafer in a cleaning solution in a dry chamber. An organic liquid vapor from an organic liquid is supplied into the dry chamber at a first volumetric supply rate to form an organic liquid layer on a surface of the cleaning solution, the organic liquid layer having at least a prescribed concentration of the organic liquid. The organic liquid vapor is supplied into the dry chamber at a second volumetric supply rate that is lower than the first volumetric supply rate. During and/or following the supplying of the organic liquid vapor into the dry chamber, at least a portion of the wafer is removed from the cleaning solution through the organic liquid layer.
    Type: Application
    Filed: January 8, 2002
    Publication date: December 26, 2002
    Inventors: Jae-Hyung Jung, Young-Min Kwon, Jong-Jae Lee, Dong-Hoon Jung
  • Publication number: 20020028585
    Abstract: A method for removing contaminants from an integrated circuit substrate include treating the substrate with a hydrogen peroxide cleaning solution containing a chelating agent, and treating the substrate with hydrogen gas and fluorine-containing gas, and annealing the substrate. Cleaning solutions includes ammonium, hydrogen peroxide, deionized water, and chelating agent. The chelating agent includes one to three compounds selected from the group consisting of carboxylic acid compounds, phosphonic acid compounds, and hydroxyl aromatic compounds. The fluorine-containing gas is a gas selected from the group consisting of nitrogen trifluoride (NF3), hexafluorosulphur (SF6), and trifluorochlorine (ClF3).
    Type: Application
    Filed: May 22, 2001
    Publication date: March 7, 2002
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seung-Pil Chung, Kyu-Hwan Chang, Young-Min Kwon, Sang-Lock Hah
  • Publication number: 20020027084
    Abstract: A wet process performed in the manufacture of semiconductor devices with cathode water and anode water produced from electrolyte using a 3-cell electrolyzer having an intermediate cell for the electrolyte. The 3-cell electrolyzer includes an anode cell, a cathode cell, and an intermediate cell between the anode and cathode cells, which are partitioned by ion exchange membranes. Deionized water is supplied into the anode and cathode cells, and the intermediate cell is filled with an electrolytic aqueous solution to perform electrolysis. The anode water containing oxidative substances or the cathode water containing reductive substances, which are produced by the electrolysis process, are used in the wet process.
    Type: Application
    Filed: September 5, 2001
    Publication date: March 7, 2002
    Inventors: Im-Soo Park, Kun-Tack Lee, Young-Min Kwon, Sang-Rok Hah, Woo-Gwan Shim, Hyung-Ho Ko
  • Publication number: 20020020887
    Abstract: A method of forming a shallow trench isolation type semiconductor device comprises forming an etch protecting layer pattern to define at least one active region on a substrate, forming at least one trench by etching the substrate partially by using the etch protecting layer pattern as an etch mask, forming a thermal-oxide film on an inner wall of the trench, filling the trench having the thermal-oxide film with a CVD silicon oxide layer to form an isolation layer, removing the etch protecting layer pattern from the substrate over which the isolation layer is formed, removing the thermal-oxide film formed on a top end of the inner wall of the trench to a depth of 100 to 350 Å, preferably 200 Å from the upper surface of the substrate, and forming a gate oxide film on the substrate from which the active region and the top end are exposed.
    Type: Application
    Filed: July 31, 2001
    Publication date: February 21, 2002
    Inventors: Keum-Joo Lee, Young-Min Kwon, Chang-Lyoung Song, In-Seak Hwang
  • Publication number: 20020003123
    Abstract: A cleaning solution for use in removing a damaged portion of a ferroelectric layer, and a cleaning method using the solution. The cleaning solution includes a fluoride, an organic acid with carboxyl group, an alkaline pH adjusting agent and water.
    Type: Application
    Filed: March 1, 2001
    Publication date: January 10, 2002
    Inventors: Kwang-wook Lee, Im-soo Park, Kun-tack Lee, Young-min Kwon, Sang-rok Hah
  • Publication number: 20020003275
    Abstract: A shallow trench type (STI) type semiconductor device employs an etch-stop layer pull-pack approach and a liner as an oxygen barrier, enhancing stability of gate insulation and reliability of transistor operation, wherein a trench sidewall thermal oxide layer with a thickness of 20 Å-140 Å is formed between silicon substrate and the liner, controlling the sidewall liner tension that acts on the substrate. This makes it possible to control the thickness of a gate insulating layer adjacent to a trench to a value equal to or greater than a value in the middle of an active region. Further, a corner adjacent to the trench is rounded to increase the voltage handling capability of device.
    Type: Application
    Filed: July 6, 2001
    Publication date: January 10, 2002
    Inventors: Keum-Joo Lee, Tai-Su Park, Young-min Kwon, Bong-Ho Moon, In-Seak Hwang, Chang-Lyoung Song
  • Publication number: 20010041455
    Abstract: A pre-stripping treatment solution for treatment of metal surfaces before stripping photoresist which has been used for patterning a metal layer. Also provided is a method of removing the photoresist, and a method of manufacturing semiconductor devices using the above solution and method. In one aspect of the invention, the photoresist is first ashed. The ashed resultant structure is then treated, prior to stripping of the photoresist, with a pre-stripping treatment solution of an organic acid solution having a carboxyl group is mixed with deionized water at a volume ratio of 1:0 to 1:100.
    Type: Application
    Filed: March 15, 1999
    Publication date: November 15, 2001
    Inventors: CHEOL-JU YUN, YOUNG-MIN KWON, HEUNG-SOO PARK
  • Publication number: 20010021565
    Abstract: A method of manufacturing a semiconductor device having a hemispherical grain (HSG) layer employs a dry cleaning process. A polysilicon layer is formed on a specific material layer on a semiconductor substrate. Next, a polysilicon pattern, at least a portion of which is exposed, is formed by etching the polysilicon layer. The exposed surface of the polysilicon pattern is then dry cleaned by supplying hydrogen in a plasma state and a fluorine-based gas toward the exposed surface. The exposed surface of the polysilicon pattern may also be wet cleaned before being dry cleaned to wash away pollutants which may have been left thereon. An HSG layer is then formed on the cleaned surface of the polysilicon pattern. After the HSG layer is formed, the surface of the HSG layer may be dry cleaned again by supplying hydrogen in a plasma state and a fluorine-based gas toward the surface of the HSG layer. The surface of the HSG layer may also be further wet cleaned before being dry cleaned.
    Type: Application
    Filed: March 6, 2001
    Publication date: September 13, 2001
    Inventors: Seung-pil Chung, Kyu-hwan Chang, Young-min Kwon, Sang-lock Hah
  • Patent number: 6117350
    Abstract: Solutions useful for etching semiconductor devices comprise ammonium fluoride, hydrofluoric acid, hydrogen peroxide, and water. Processes for forming the solutions comprise mixing first solutions which comprise ammonium fluoride, hydrofluoric acid, and water with second solutions which comprise hydrogen peroxide and water to form the solutions of the invention. Methods for etching semiconductor devices comprise contacting the devices which comprise a substrate and oxide layer thereon with the solutions of the invention to etch the devices. The oxide layer, for example a damaged silicon oxide layer on a silicon substrate, is selectively etched to the substrate.
    Type: Grant
    Filed: July 19, 1996
    Date of Patent: September 12, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung-moon Yoon, Young-min Kwon, Yong-sun Ko, Myung-jun Park