Patents by Inventor Young-Mok Kim

Young-Mok Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170196955
    Abstract: The present invention relates to a method for preparing a dendritic cell, a dendritic cell prepared thereby and a use thereof, and more specifically, to a method for preparing a dendritic cell, including: treating a dendritic cell at a maturation stage rather than at an immature stage with an antigen bound to a peptide having a cell membrane permeability to prepare a dendritic cell with improved antigen-presenting ability, a dendritic cell prepared by the method, and an immunotherapeutic agent thereof, a use for anti-tumor vaccines, or a pharmaceutical composition for treating tumors, containing the same.
    Type: Application
    Filed: July 28, 2015
    Publication date: July 13, 2017
    Inventors: Yoon Lee, Young-Mok Kim, So-Yeon Kim, Seung-Soo Han, Yong-Soo Bae
  • Patent number: 9701942
    Abstract: The present invention relates to a composition for maturing dendritic cells, comprising, as a maturation-promoting factor, Interleukin-1? (IL-1?), Interleukin-6 (IL-6), Tumor necrosis factor-? (TNF-?), Interferon-? (IFN-?), Prostaglandin E2 (PGE2), Picibanil (OK432) and/or Poly IC. The composition for maturing dendritic cells of the present invention may have the effects of not only improving the ability of dendritic cells to induce an immune response, but also of decreasing the antigen non-specific immune response of dendritic cells and increasing antigen-specific immune response of dendritic cells, thus maximizing the effects of immunotherapy.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: July 11, 2017
    Assignee: JW CREAGENE INC.
    Inventors: Yoon Lee, Hye-Won Kang, Seung-Soo Han, Young-Mok Kim, Yong-Soo Bae, Seo-Hee Ahn
  • Publication number: 20170131832
    Abstract: An electronic device is provided. The electronic device includes an input panel configured to periodically sense touch coordinates corresponding to a touch manipulation of a user; and a processor configured to periodically receive the touch coordinates from the input panel, calculate a variation of the touch coordinates based on the touch coordinates, change a reference value for determining movement of the touch manipulation based on the variation of the touch coordinates, and determine whether the touch manipulation moves, based on the reference value.
    Type: Application
    Filed: November 4, 2016
    Publication date: May 11, 2017
    Inventors: Sung Jun LEE, Jae Min LEE, Seung Jin KIM, Jun Ik LEE, Ki Won KIM, Young Mok KIM
  • Publication number: 20160239148
    Abstract: A method of controlling an activation area of a touch screen panel and an electronic device using the same. A method of operating an electronic device, according to an embodiment of the present disclosure, may include: setting a partial area of a touch screen panel, which corresponds to a view window of a cover that is mounted on the electronic device, as an effective touch area when the cover is closed; and when the cover mounted on the electronic device is closed, activating the partial area of the touch screen panel that corresponds to the set effective touch area. In addition, the various embodiments of the present disclosure also include other embodiments as well as the above-described embodiment.
    Type: Application
    Filed: February 17, 2016
    Publication date: August 18, 2016
    Inventors: Jeong-Jin Lee, Mooyoung Kim, Young Mok Kim
  • Publication number: 20150125956
    Abstract: The present invention relates to a composition for maturing dendritic cells, comprising, as a maturation-promoting factor, Interleukin-1? (IL-1?), Interleukin-6 (IL-6), Tumor necrosis factor-? (TNF-?), Interferon-? (IFN-?), Prostaglandin E2 (PGE2), Picibanil (OK432) and/or Poly IC. The composition for maturing dendritic cells of the present invention may have the effects of not only improving the ability of dendritic cells to induce an immune response, but also of decreasing the antigen non-specific immune response of dendritic cells and increasing antigen-specific immune response of dendritic cells, thus maximizing the effects of immunotherapy.
    Type: Application
    Filed: May 30, 2013
    Publication date: May 7, 2015
    Applicant: JW CREAGENE INC.
    Inventors: Yoon Lee, Hye-Won Kang, Seung-Soo Han, Young-Mok Kim, Yong-Soo Bae, Seo-Hee Ahn
  • Publication number: 20150044316
    Abstract: The present invention relates to a method for preparing a purified extract of Lonicera Japonica THUNBERG and the composition comprising the same for preventing and treating sepsis and septic shock. The purified extract of purified extract of Lonicera Japonica THUNBERG potent antisepsis activity in severe sepsis CLP model test, the effect on MODS, and the inhibitory effect on various pro-inflammatory cytokines such as TNF-alpha, IL-1beta, IFN-gamma, HMGB-1 etc, as well as it showed unexpectedly synergistic effect on the treatment of sepsis and septic shock in case of combining with the commercially available anti-septic agent such as broad-spectrum anti-biotic to the person skilled in the art, therefore, it can be useful in treating and preventing the sepsis and septic shock as a medicament and health functional food.
    Type: Application
    Filed: November 1, 2012
    Publication date: February 12, 2015
    Inventors: Sung-Tae Yoon, Jeong Hoon Kim, Bang Ho Lim, Young Mok Kim, Sung Hum Yeon, Hyun Soo Kim, Sun-Mee Lee
  • Publication number: 20140055160
    Abstract: An apparatus and method for inspecting whether marking of a target chip in a wafer has been performed normally are provided. The apparatus includes a voltage application detector which detects application of a voltage to an external circuit, an image pickup unit which captures an image, and a controller which controls the image pickup unit to capture an image at at least one predetermined point when the application of the voltage is detected by the voltage application detector and determines whether the marking of the target chip has been performed normally based on the captured image. Accordingly, extra time is not required to inspect whether the marking of the target chip in the wafer has been performed normally and the inspection is performed without using a prober operation program.
    Type: Application
    Filed: August 15, 2013
    Publication date: February 27, 2014
    Applicant: Korea Hugle Electronics Inc.
    Inventors: Young Mok Kim, Hyoung Woo Bae
  • Patent number: 8476700
    Abstract: A semiconductor device comprises a recessed trench in a substrate, a gate insulating layer including a first portion and a second portion, the first portion having a first thickness and covering lower portions of sidewalls of the recessed trench and a bottom surface of the recessed trench, and the second portion having a second thickness and covering upper portions of the sidewalls of the recessed trench, the second thickness being greater than the first thickness, a gate electrode filling the recessed trench, a first impurity region having a first concentration and disposed at opposing sides of the gate electrode, and a second impurity region having a second concentration greater than the first concentration and disposed on the first impurity region to correspond to the second portion of the gate insulating layer.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: July 2, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Mok Kim, Sun-Hak Lee, Tae-Cheol Lee, Yong-Sang Jeong
  • Patent number: 8101482
    Abstract: Provided is a method of fabricating a semiconductor device having a transistor. The method includes forming a first gate trench in a first active region of a semiconductor substrate. A first gate layer partially filling the first gate trench is formed. Ions may be implanted in the first gate layer and in the first active region on both sides of the first gate layer such that the first gate layer becomes a first gate electrode of a first conductivity type and first impurity regions of the first conductivity type are formed on both sides of the first gate electrode.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: January 24, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-Mok Kim
  • Publication number: 20110278662
    Abstract: A semiconductor device including a recessed channel transistor, and a method of manufacturing the same, provide: a substrate in which an isolation trench is provided; an isolation layer provided in the isolation trench so as to define a pair of source/drain regions in the substrate; a gate pattern provided in the isolation trench between the pair of source/drain regions, the gate pattern having a top surface at a same level as a top surface of the isolation layer and having a bottom surface at a lower depth than the pair of source/drain regions with respect to a top surface of the substrate; and a gate insulating layer provided between the substrate and the gate pattern at a bottom surface of the isolation trench.
    Type: Application
    Filed: April 28, 2011
    Publication date: November 17, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-il Park, Joon-ho Cho, Tae-cheol Lee, Yong-sang Jeong, Eun-jeong Park, Young-mok Kim, Seok-ju Lee
  • Publication number: 20110109828
    Abstract: Recessed channel transistor (RCT) devices, methods of manufacturing the RCT devices, and a display apparatuses including the RCT devices. A RCT device includes a substrate, a first trench in the substrate and having a first width; a first gate insulating layer on an inner wall of the first trench; a first recess gate on the first gate insulating layer and having a groove in a center portion of an upper surface of the first recess gate; and a source and drain in the substrate on both sides of the first recess gate.
    Type: Application
    Filed: June 10, 2010
    Publication date: May 12, 2011
    Inventors: Young-mok Kim, Yong-sang Jeong, Tae-cheol Lee
  • Publication number: 20100207204
    Abstract: A semiconductor device comprises a recessed trench in a substrate, a gate insulating layer including a first portion and a second portion, the first portion having a first thickness and covering lower portions of sidewalls of the recessed trench and a bottom surface of the recessed trench, and the second portion having a second thickness and covering upper portions of the sidewalls of the recessed trench, the second thickness being greater than the first thickness, a gate electrode filling the recessed trench, a first impurity region having a first concentration and disposed at opposing sides of the gate electrode, and a second impurity region having a second concentration greater than the first concentration and disposed on the first impurity region to correspond to the second portion of the gate insulating layer.
    Type: Application
    Filed: February 12, 2010
    Publication date: August 19, 2010
    Inventors: Young-Mok Kim, Sun-Hak Lee, Tae-Cheol Lee, Yong-Sang Jeong
  • Publication number: 20100197090
    Abstract: Provided is a method of fabricating a semiconductor device having a transistor. The method includes forming a first gate trench in a first active region of a semiconductor substrate. A first gate layer partially filling the first gate trench is formed. Ions may be implanted in the first gate layer and in the first active region on both sides of the first gate layer such that the first gate layer becomes a first gate electrode of a first conductivity type and first impurity regions of the first conductivity type are formed on both sides of the first gate electrode.
    Type: Application
    Filed: February 3, 2010
    Publication date: August 5, 2010
    Inventor: Young-Mok Kim
  • Publication number: 20080014708
    Abstract: Disclosed is a method of fabricating a semiconductor device having improved processing stability. A protection layer may be formed on a semiconductor substrate. A sacrificial layer having an etch selectivity with respect to the protection layer may be formed on the protection layer. A part of the sacrificial layer may be selectively etched, thereby forming an alignment key. An aligned well may be formed using the alignment key. An aligned isolation layer may be formed in the semiconductor substrate having the well formed therein, using the alignment key.
    Type: Application
    Filed: June 25, 2007
    Publication date: January 17, 2008
    Inventor: Young-mok Kim
  • Publication number: 20020147995
    Abstract: Disclosed is a method of setting up an output format of a set-top box matching an output format of a set-top box identically with that of a display device if the output formats of the set-top box and display device fail to be identical to each other. The present invention includes the steps of setting up preliminarily an output format of the set-top box as one of a plurality of formats the set-top box enables to output, outputting a predetermined message with the preliminary setup output format from the set-top box to a display device connected to the set-top box, informing, if the predetermined message is displayed on the display device, the set-top box of the message display, and fixing the preliminary setup output format to the output format of the set-top box, wherein the output format of the set-top box is made to coincide with an output format of the display device if the output formats of the set-top box and display device are different from each other.
    Type: Application
    Filed: April 5, 2002
    Publication date: October 10, 2002
    Inventors: Jeong Min Kim, Young Mok Kim