Abstract: A method of manufacturing a semiconductor device, the method including providing a semiconductor substrate; forming a gate pattern on the semiconductor substrate such that the gate pattern includes a gate dielectric layer and a sacrificial gate electrode; forming an etch stop layer and a dielectric layer on the semiconductor substrate and the gate pattern; removing portions of the dielectric layer to expose the etch stop layer; performing an etch-back process on the etch stop layer to expose the sacrificial gate electrode; removing the sacrificial gate electrode to form a trench; forming a metal layer on the semiconductor substrate including the trench; removing portions of the metal layer to expose the dielectric layer; and performing an etch-back process on the metal layer to a predetermined target.

Abstract: A method of fabricating an image sensor according to example embodiments may include forming a photodiode in a photoelectric conversion region of a substrate and forming an etch stop layer on the substrate. The etch stop layer may be patterned to form an inner lens on the photoelectric conversion region and an etch stop layer pattern on a transistor region of the substrate. A metal interconnection structure may be formed on the inner lens and the etch stop layer pattern. Accordingly, the number of additional processes for fabricating an image sensor may be reduced.

Abstract: Methods of forming dual-damascene metal interconnect structures include forming an electrically insulating layer on an integrated circuit substrate and then forming a hard mask layer on the electrically insulating layer. The hard mask layer may include a stacked composite of at least four electrically insulating material layers therein. The hard mask layer may also have separate trench and via patterns therein that are respectively defined by at least first and second ones of the electrically insulating material layers and at least third and fourth ones of the electrically insulating material layers.

Abstract: Methods of forming dual-damascene metal interconnect structures include forming an electrically insulating layer on an integrated circuit substrate and then forming a hard mask layer on the electrically insulating layer. The hard mask layer may include a stacked composite of at least four electrically insulating material layers therein. The hard mask layer may also have separate trench and via patterns therein that are respectively defined by at least first and second ones of the electrically insulating material layers and at least third and fourth ones of the electrically insulating material layers.

Abstract: A method of fabricating an image sensor according to example embodiments may include forming a photodiode in a photoelectric conversion region of a substrate and forming an etch stop layer on the substrate. The etch stop layer may be patterned to form an inner lens on the photoelectric conversion region and an etch stop layer pattern on a transistor region of the substrate. A metal interconnection structure may be formed on the inner lens and the etch stop layer pattern. Accordingly, the number of additional processes for fabricating an image sensor may be reduced.

Abstract: A dry etching method comprises placing a semiconductor substrate in a reactor, the semiconductor substrate comprising a photoresist pattern formed on an etching target layer, supplying carbon monoxide gas into the reactor to selectively deposit polymer on the photoresist pattern to form a polymer layer, and etching the etching target layer using the photoresist pattern and the polymer layer as an etch mask.