Abstract: A semiconductor device is provided. The semiconductor device includes: a first active pattern extending in a first direction; a second active pattern spaced apart extending in the first direction, the first active pattern being provided between the second active pattern and a substrate; a gate structure extending in a second direction, the first active pattern and the second active pattern passing through the gate structure, and the second direction crossing the first direction; a first source/drain area connected with the first active pattern and provided on a side of the gate structure; a second source/drain area connected with the second active pattern and provided on the first source/drain area; a first insulating structure provided between the substrate and the first source/drain area, the first insulating structure not being provided between the substrate and the gate structure; and a second insulating structure provided between the first source/drain area and the second source/drain area.

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction. The semiconductor device includes an epitaxial layer on the active portions. The semiconductor device includes a metal silicide layer on the epitaxial layer. Moreover, the semiconductor device includes a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer. Related methods of forming semiconductor devices are also provided.

Abstract: Semiconductor devices may include a plurality of active fins each extending in a first direction on a substrate, a gate structure extending on the active fins in a second direction, and a first source/drain layer on first active fins of the active fins adjacent the gate structure. At least one of two opposing sidewalls of a cross-section of the first source/drain layer taken along the second direction may include a curved portion having a slope with respect to an upper surface of the substrate. The slope may decrease from a bottom toward a top thereof.

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction. The semiconductor device includes an epitaxial layer on the active portions. The semiconductor device includes a metal silicide layer on the epitaxial layer. Moreover, the semiconductor device includes a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer. Related methods of forming semiconductor devices are also provided.

Abstract: Semiconductor devices may include a plurality of active fins each extending in a first direction on a substrate, a gate structure extending on the active fins in a second direction, and a first source/drain layer on first active fins of the active fins adjacent the gate structure. At least one of two opposing sidewalls of a cross-section of the first source/drain layer taken along the second direction may include a curved portion having a slope with respect to an upper surface of the substrate. The slope may decrease from a bottom toward a top thereof.

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction. The semiconductor device includes an epitaxial layer on the active portions. The semiconductor device includes a metal silicide layer on the epitaxial layer. Moreover, the semiconductor device includes a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer. Related methods of forming semiconductor devices are also provided.

Abstract: Semiconductor devices may include a plurality of active fins each extending in a first direction on a substrate, a gate structure extending on the active fins in a second direction, and a first source/drain layer on first active fins of the active fins adjacent the gate structure. At least one of two opposing sidewalls of a cross-section of the first source/drain layer taken along the second direction may include a curved portion having a slope with respect to an upper surface of the substrate. The slope may decrease from a bottom toward a top thereof.

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction. The semiconductor device includes an epitaxial layer on the active portions. The semiconductor device includes a metal silicide layer on the epitaxial layer. Moreover, the semiconductor device includes a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer. Related methods of forming semiconductor devices are also provided.

Abstract: Semiconductor devices may include a plurality of active fins each extending in a first direction on a substrate, a gate structure extending on the active fins in a second direction, and a first source/drain layer on first active fins of the active fins adjacent the gate structure. At least one of two opposing sidewalls of a cross-section of the first source/drain layer taken along the second direction may include a curved portion having a slope with respect to an upper surface of the substrate. The slope may decrease from a bottom toward a top thereof.

Abstract: A solar cell includes a crystalline photovoltaic layer, a first impurity region having a first conductivity type and a second impurity region having a second conductivity type in the photovoltaic layer, a third impurity region having the first conductivity type in the first impurity region, a fourth impurity region having the second conductivity type in the second impurity region, a first barrier layer and a second barrier layer contacting the third impurity region and the fourth impurity region, respectively, and a first electrode and a second electrode contacting the first barrier layer and the second barrier layer, respectively. The first impurity region and the second impurity region are spaced apart from each other. The third impurity region and the fourth impurity region have an impurity concentration higher than the first impurity region the second impurity region, respectively.

Abstract: A solar cell may include a PN junction including a semiconductor substrate of a first conductivity and an emitter of a second conductivity, a passivation layer on an exposed surface of the semiconductor substrate, a first electrode connected to the semiconductor substrate, and a second electrode connected to the emitter. The passivation layer may be configured to apply stress to the exposed surface of the substrate such that a mobility of minority charge carriers in the semiconductor substrate is decreased in a first direction perpendicular to a boundary surface of the semiconductor substrate and the passivation layer.

Abstract: A solar cell includes a semiconductor layer including a charge carrier produced therein upon exposure to light, and a passivation layer on a side of the semiconductor layer, the passivation layer configured to apply a stress to the semiconductor layer and change a mobility of the charge carrier into a direction in the semiconductor layer.

Abstract: According to example embodiments, a solar cell includes a photoelectric member on a passivation member. The photoelectric member is configured to convert incident light into current. The passivation member includes protection material for protecting the-photoelectric member and wavelength conversion material configured to convert light that passes through the photoelectric member into different wavelength.

Abstract: Provided are methods of forming patterns of semiconductor devices, whereby patterns having various widths may be simultaneously formed, and a pattern density may be doubled by a double patterning process in a portion of the semiconductor device. A dual mask layer is formed on a substrate. A variable mask layer is formed on the dual mask layer. A first photoresist pattern having a first thickness and a first width in the first region, and a second photoresist pattern having a second thickness greater than the first thickness and a second width wider than the first width in the second region are formed on the variable mask layer. A first mask pattern and a first variable mask pattern are formed in the first region, and a second mask pattern and a second variable mask pattern are formed in the second region, by sequentially etching the variable mask layer and the dual mask layer by using, as etch masks, the first photoresist pattern and the second photoresist pattern.

Abstract: According to example embodiments, a solar cell includes a first unit portion, a second unit portion, and an insulating layer. The first and second unit portions may have different bandgaps, and the insulating layer may be between the first unit portion and the second unit portion.

Abstract: According to example embodiments, a solar cell includes a plurality of unit portions. Each of the unit portions may have a stacked structure including a plurality of photoelectric members and at least one insulating layer disposed between the photoelectric members. The photoelectric members in different levels may have different energy bandgaps. The photoelectric members in a level may be connected to each other.

Abstract: Example embodiments of a solar cell including a semiconductor substrate, an N emitter layer formed on a light-absorbing surface of the semiconductor substrate, a p+ region formed on the light-absorbing surface of the semiconductor substrate, a first electrode electrically connected to the p+ region, a second electrode separately formed from the first electrode on the light-absorbing surface of the semiconductor substrate and electrically connected to the N emitter layer, and an auxiliary layer inducing an N+ back surface field (BSF) on the opposite surface to the light-absorbing surface of the semiconductor substrate, and a method of manufacturing the solar cell are provided.

Abstract: In a method of forming carbon nano-tubes, a catalytic film is formed on a substrate. The catalytic film is then transformed into preliminary catalytic particles. Thereafter, the preliminary catalytic particles are transformed into catalytic particles. Carbon nano-tubes then grow from the catalytic particles. The carbon nano-tubes have relatively high conductivity and high number density.

Abstract: A device includes an insulating layer on a substrate having a lower conductive pattern, the insulating layer having a contact hole that penetrates the insulating layer and exposes a portion of the lower conductive pattern, a catalytic pattern having a first portion on the exposed portion of the lower conductive pattern and a second portion on a sidewall of the contact hole, a spacer on the sidewall of the contact hole, wherein the second portion of the catalytic pattern is disposed between the spacer and the sidewall, and a contact plug in the contact hole and contacting the catalytic pattern, the contact plug being a carbon nanotube material.

Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device, for example, a semiconductor device using carbon nanotubes or nanowires as lower electrodes of a capacitor, and a method of manufacturing the semiconductor device. The semiconductor device may include a lower electrode including a plurality of tubes or wires on a semiconductor substrate, a dielectric layer on the surface of the lower electrode, and an upper electrode on the surface of the dielectric layer, wherein the plurality of tubes or wires radiate outwardly from each other centering on the lower portion of the plurality of tubes or wires. Thus, the off current of the capacitor may be increased by increasing the surface area of the lower electrodes of the capacitor.