Abstract: An MPEG2 moving picture and encoding/decoding system to provide digital copy protection of digital moving picture data. The MPEG2 moving picture encoder discrete cosine transforms a video input signal and uses a digital watermark inserter to embed digital watermark information on a frequency domain of the discrete cosine transformed video input signal. The MPEG2 moving picture decoder receives the encoded video output signal from the MPEG2 moving picture encoder and removes the embedded visual watermark information to locally decode the encoded video signal.

Abstract: There is disclosed an option function test apparatus of a semiconductor device including a function selecting means. The function selection means includes a fuse signal detecting section for sensing the state of fuse blowing, a pad signal detecting section for sensing the signal state on the probe pad for selecting its specification, which is consisted by incorporating extra probe chips into the existing probe card, and a global signal control section for receiving the output signals from said fuse signal detecting section and said pad signal detecting section to output different output signals based on its operation mode. Thus, the present invention can provide an outstanding effect of reducing additional test time and cost depending on the changes in function, since it allows a multifunction test of all of the specifications mounted on the on-chip in a wafer state.

Abstract: An internal voltage fall-down circuit includes a reference voltage generating section for variably generating an optimum reference voltage level of which is compensated for depending on changes in the present reference voltage before fuse blowing, a reference voltage transforming section for receiving the reference voltage from the reference voltage generating section and then transforming the reference voltage into voltage for a normal mode or a stress mode which are presently set, and a driver section for providing a signal from the reference voltage transforming section to an internal circuit as an internal supply voltage.

Abstract: The present invention is directed to a wordline driving apparatus in semiconductor memory devices. The wordline driving apparatus comprises a CMOS distributed type sub-wordline driver for receiving an output signal of a row decoder through a main wordline having a wiring structure of a single output line and controlling enabling of the sub-wordline in accordance with the received output signal and a sub pull-down driver for receiving the inverted signals of boosting signals through a control signal supplying wiring and performing a sub pull-down function with respect to the voltage level of the sub-wordline. According to the present invention, it is possible to greatly improve an access time with enhancing a high voltage transfer efficiency and preventing a delay of signal.

Abstract: A redundant circuit for a semiconductor device including a fuse program means producing a control signal determining whether or not a chip is normal; a high-voltage generating means producing a first voltage or second voltage according to a control signal from the fuse program means; and an on-chip redundant decoding means driven by the first voltage or second voltage produced from the high-voltage generating means. In case that the chip is normal, the high-voltage generating means generates the first voltage, and in case that the chip fails, the high-voltage generating means produces the second voltage. The first voltage is an output voltage from the high-voltage generating means, and the second voltage is an output voltage higher than the first voltage.

Abstract: A ring oscillator generates a pulse signal having a frequency determined in response to a level change in the source voltage.

Abstract: A semiconductor memory device operates at a high speed by applying high-voltage used for driving word lines in accordance with an activated state of a bank by using a high-voltage circuit controlled for each bank or by inserting control circuits in each output stage of the high-voltage circuit in the memory device adopting a number of banks. The memory device includes a high-voltage generation circuit that includes a number of unit high-voltage generation circuits that output a high-voltage of the same level, and a multi-bank circuit that includes a number of unit bank circuits driven independently in response to the high-voltage signal of a corresponding unit high-voltage generation circuit, a corresponding row decoder output signal and a corresponding column decoder output signal.

Abstract: An analog-to-digital (A/D) conversion apparatus using a delta-sigma method performs a magnitude control operation and a filtering operation with respect to a differential signal in a conventional A/D conversion apparatus. The A/D conversion apparatus includes a multiplier for multiplying a differential signal output from a differential circuit, a filter for filtering the differential signal and outputting a filtered data signal, and an adder for adding the signals output from the multiplier and the filter and supplying the added result to a quantizer. The factor used in the multiplier is selected so that the quantization noise generated is smaller than the quantization noise generated in the conventional A/D conversion apparatus. Thus, the A/D conversion apparatus provides a wider bandwidth than the conventional A/D conversion apparatus, since it generates relatively smaller quantization noise with respect to the entire passband.

Abstract: A synchronous dynamic random access memory (DRAM) for stabilizing a redundant operation prevents a redundant decoder's malfunction which occurs in a step of latching a redundant decoder according to a fuse programmable information during a power-up time.

Abstract: A column decoder array device used in a synchronous graphic random access memory, in which column decoders adapted to simultaneously operate for a block write function are arranged in a laterally symmetrical manner or in a shifted manner, so as to effectively reduce the intensity of peak current.

Abstract: A digital audio recording apparatus for formatting digital audio data and recording formatted data on a digital recording medium, so that digital audio data having a first sampling frequency and other digital audio data having a second sampling frequency being twice the first sampling frequency, can be reproduced in both a reproduction apparatus having an operating frequency, for digital-to-analog converting the first sampling frequency and that having an operating frequency for digital-to-analog converting the second sampling frequency. The digital audio recording apparatus transforms the digital audio data into transformation coefficients in a frequency domain, the transformation coefficients are formatted using one of predetermined recording formats.

Abstract: A multiple level voltage generator for a semiconductor memory device, comprising a back bias voltage charge pumping circuit for pumping charge to a back bias voltage node, a back bias voltage level detector for detecting the level of a back bias voltage at the back bias voltage node and generating first and second back bias voltage detection signals in accordance with the detected result, a high voltage charge pumping circuit for pumping charge to a high voltage node, a high voltage level detector for detecting the level of a high voltage at the high voltage node and generating first and second high voltage detection signals in accordance with the detected result, a control logic circuit for generating a control signal in response to the second back bias voltage detection signal from the back bias voltage level detector and the second high voltage detection signal from the high voltage level detector, and an oscillator for generating first and second output signals in response to the control signal from the c

Abstract: A bit line sense amplifier array for a semiconductor memory device which has a memory cell array with at least two memory cells sharing a metal strapping region, and a plurality of true and complementary bit lines for transferring data from the at least two memory cells externally or transferring external data to the at least two memory cells. The bit line sense amplifier array comprises at least one sense amplifier block for sensing and amplifying data on the true and complementary bit lines.

Abstract: A recording and reproducing system for a digital VTR for home use, to record video and aural signals onto the same track of tape, by adding stereo aural signals to digital video component signals, and to reproduce digital component signals and stereo aural signals recorded on the same track of the tape by way of separation. The system includes an aural signal adder adding respective stereo aural signals that were converted to digital signals through A/D converters onto data which are transmitted from image encoder under compression, and error correction encoders generating data transmitted from the aural signal encoders by adding error correction bits, and an aural signal separator separating stereo aural data from data generated from error correction decoder, and a D/A converter for converting aural signal separator signals into analog signals.