Abstract: An improved precharge voltage generator for a semiconductor memory device having a bit line connected to a plurality of memory cell arrays. The improved precharge voltage generator employs a voltage divider for dividing a supply voltage and supplying the divided voltage as a precharge voltage signal to the bit line, and a first control current sink connected in parallel to the voltage divider to increase an amount of current of the precharge voltage signal to be supplied to the bit line in an active mode of the semiconductor memory device. The improved precharge voltage generator can use a second control current sink connected in parallel to the voltage divider to increase the current amount of the precharge voltage signal to be supplied to the bit line for a predetermined time period from an end time point of the active mode of the semiconductor memory device.

Abstract: A bit line sense amplifier circuit for restoring and sensing data on a bit line in a semiconductor device. The bit line sense amplifier circuit comprises a first restore signal circuit including a PMOS transistor. The PMOS transistor is operated in response to a first clock signal. The bit line sense amplifier circuit further comprises a first sensing signal circuit including an NMOS transistor. The NMOS transistor is operated in response to a second clock signal. The bit line sense amplifier circuit further comprises a second restore signal circuit being operated in response to a first control signal and a third clock signal, and a second sensing signal circuit being operated in response to a second control signal and a fourth clock signal. The first and second restore signal circuits are connected in parallel to each other. Similarly, the first and second sensing signal circuits are connected in parallel to each other.

Abstract: A ring oscillator for a semiconductor device comprising a ring oscillation circuit for generating a pulse signal according to a logic state of a control signal, the pulse signal having a predetermined period and a reduced operating voltage level, a comparator for comparing the pulse signal from the ring oscillation circuit with a reference voltage signal according to the logic state of the control signal and amplifying it in accordance with the compared result, and a driver for buffering an output signal from the comparator. The ring oscillation circuit includes an inverter chain for supplying the pulse signal with the reduced operating voltage level. According to the present invention, power consumption can significantly be reduced in the ring oscillation circuit.

Abstract: A data output buffer comprising a pull-up driver connected between a first voltage source and a data output line, for amplifying a first logic value of an input data signal, a pull-down driver connected between a second voltage source and the data output line, for amplifying a second logic value of the input data signal, a pull-down driver connection circuit connected between the pull-down driver and the second voltage source, for varying an impedance of the pull-down driver, and a pull-down driver control circuit for detecting whether the input data signal has its second logic value and generating a control signal in accordance with the detected result to control the operation of the pull-down driver connection circuit. According to the present invention, the data output buffer can control an amount of current flowing through the pull-down driver in a multi-step manner to minimize an impulse noise component in low logic output data on the data output line.

Abstract: An improved bootstrap circuit comprising a booster for boosting a binary signal and outputting the boosted binary signal through its output terminal, a voltage detector for detecting a variation of a supply voltage from a supply voltage source, and an active load for adjusting an output load amount of the booster under control of the voltage detector. According to the present invention, the binary signal is boosted to a voltage level which is stable regardless of the variation of the supply voltage.

Abstract: A voltage down converter for a semiconductor memory device which includes memory blocks for storing a plurality of binary information, memory peripheral circuits for controlling the memory blocks and a reference voltage generator for dividing a supply voltage from an external power supply circuit to drive the memory blocks and the memory peripheral circuits.

Abstract: A data output equipment for a semiconductor memory device is disclosed. The data output equipment makes a reading data from a memory cell to output via a data output buffer when a data output buffer enable signal generated by a detect signal from a fuse programmable delay controller or a bond pad is applied to the data output buffer.