Patents by Inventor Young-Ock HONG
Young-Ock HONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11587941Abstract: A method of manufacturing a semiconductor device includes forming a stacked structure including trenches having different depths, forming an insulating layer on the stacked structure to fill the trenches, and forming a plurality of protrusions located corresponding to locations of the trenches by patterning the insulating layer. The method also includes forming insulating patterns filling the trenches, respectively, by planarizing the patterned insulating layer including the plurality of protrusions.Type: GrantFiled: April 16, 2020Date of Patent: February 21, 2023Assignee: SK hynix Inc.Inventors: Byung Woo Kang, Sae Jun Kwon, Hwal Pyo Kim, Jin Taek Park, Yang Seok Lim, Young Ock Hong
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Patent number: 11574920Abstract: A semiconductor device includes: a stack structure including a cell region and a contact region; a channel structure penetrating the cell region of the stack structure; trenches penetrating the contact region of the stack structure to different depths; and a stop structure penetrating the contact region of the stack structure, the stop structure being located between the trenches.Type: GrantFiled: May 11, 2020Date of Patent: February 7, 2023Assignee: SK hynix Inc.Inventors: Byung Woo Kang, Sae Jun Kwon, Seung Min Lee, Hwal Pyo Kim, Jin Taek Park, Seung Woo Han, Young Ock Hong
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Patent number: 11508747Abstract: A semiconductor memory device includes: a stacked structure including first and second select patterns spaced apart from each other in a first direction; a gate isolation layer extending in a second direction intersecting the first direction between the first and second select patterns; channel structures penetrating the stack structure; and first and second bit lines extending in the first direction, the first and second bit lines being adjacent to each other. The channel structures include: a first channel structure which penetrates the first select pattern and is spaced apart by a first distance from the gate isolation layer in the first direction; and a second channel structure which penetrates the second select pattern and is spaced apart by substantially the first distance from the gate isolation layer in the first direction. The first and second channel structures are respectively connected to the second and first bit lines.Type: GrantFiled: May 6, 2020Date of Patent: November 22, 2022Assignee: SK hynix Inc.Inventors: Young Ock Hong, Eun Seok Choi
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Patent number: 11456312Abstract: A semiconductor memory device includes a substrate including a peripheral circuit; an interconnection array disposed on the peripheral circuit; a cell stack structure disposed on the interconnection array, the cell stack structure including gate electrodes stacked in a vertical direction to form a cell step structure; and a dummy stack structure disposed on the interconnection array, the dummy stack structure including sacrificial layers stacked in the vertical direction to form a dummy step structure parallel to the cell step structure. The interconnection array includes a first lower conductive pattern including a center region overlapping with a slit between the cell step structure and the dummy step structure, a first region extending to overlap with the dummy step structure from the center region, and a second region extending to overlap with the cell step structure from the center region.Type: GrantFiled: May 4, 2020Date of Patent: September 27, 2022Assignee: SK hynix Inc.Inventor: Young Ock Hong
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Patent number: 11362104Abstract: A semiconductor memory device includes a substrate including a peripheral circuit, a stepped dummy stack overlapping the substrate and including a plurality of steps extending in a first direction, a plurality of contact groups passing through the stepped dummy stack, and upper lines respectively connected to the contact groups. The contact groups include a first contact group having two or more first contact plugs arranged in the first direction. The upper lines include a first upper line commonly connected to the first contact plugs.Type: GrantFiled: June 30, 2020Date of Patent: June 14, 2022Assignee: SK hynix Inc.Inventors: Byung Woo Kang, Min Sung Ko, Gwang Been Kim, Hwal Pyo Kim, Jin Taek Park, Young Ock Hong
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Patent number: 11195851Abstract: The present technology provides a semiconductor memory device. The semiconductor memory device includes a source film spaced from a substrate and disposed on the substrate, a conductive contact plug penetrating the source film, and a dummy stack body including dummy interlayer insulating films and sacrificial insulating films alternately stacked on the conductive contact plug.Type: GrantFiled: October 31, 2019Date of Patent: December 7, 2021Assignee: SK hynix Inc.Inventors: Jae Taek Kim, Young Ock Hong
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Publication number: 20210159245Abstract: A semiconductor memory device includes: a stacked structure including first and second select patterns spaced apart from each other in a first direction; a gate isolation layer extending in a second direction intersecting the first direction between the first and second select patterns; channel structures penetrating the stack structure; and first and second bit lines extending in the first direction, the first and second bit lines being adjacent to each other. The channel structures include: a first channel structure which penetrates the first select pattern and is spaced apart by a first distance from the gate isolation layer in the first direction; and a second channel structure which penetrates the second select pattern and is spaced apart by substantially the first distance from the gate isolation layer in the first direction. The first and second channel structures are respectively connected to the second and first bit lines.Type: ApplicationFiled: May 6, 2020Publication date: May 27, 2021Applicant: SK hynix Inc.Inventors: Young Ock HONG, Eun Seok CHOI
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Publication number: 20210134823Abstract: A semiconductor memory device includes a substrate including a peripheral circuit, a stepped dummy stack overlapping the substrate and including a plurality of steps extending in a first direction, a plurality of contact groups passing through the stepped dummy stack, and upper lines respectively connected to the contact groups. The contact groups include a first contact group having two or more first contact plugs arranged in the first direction. The upper lines include a first upper line commonly connected to the first contact plugs.Type: ApplicationFiled: June 30, 2020Publication date: May 6, 2021Applicant: SK hynix Inc.Inventors: Byung Woo KANG, Min Sung KO, Gwang Been KIM, Hwal Pyo KIM, Jin Taek PARK, Young Ock HONG
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Publication number: 20210098476Abstract: A semiconductor memory device includes a substrate including a peripheral circuit; an interconnection array disposed on the peripheral circuit; a cell stack structure disposed on the interconnection array, the cell stack structure including gate electrodes stacked in a vertical direction to form a cell step structure; and a dummy stack structure disposed on the interconnection array, the dummy stack structure including sacrificial layers stacked in the vertical direction to form a dummy step structure parallel to the cell step structure. The interconnection array includes a first lower conductive pattern including a center region overlapping with a slit between the cell step structure and the dummy step structure, a first region extending to overlap with the dummy step structure from the center region, and a second region extending to overlap with the cell step structure from the center region.Type: ApplicationFiled: May 4, 2020Publication date: April 1, 2021Applicant: SK hynix Inc.Inventor: Young Ock HONG
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Publication number: 20210091109Abstract: A semiconductor device includes: a stack structure including a cell region and a contact region; a channel structure penetrating the cell region of the stack structure; trenches penetrating the contact region of the stack structure to different depths; and a stop structure penetrating the contact region of the stack structure, the stop structure being located between the trenches.Type: ApplicationFiled: May 11, 2020Publication date: March 25, 2021Applicant: SK hynix Inc.Inventors: Byung Woo KANG, Sae Jun KWON, Seung Min LEE, Hwal Pyo KIM, Jin Taek PARK, Seung Woo HAN, Young Ock HONG
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Publication number: 20210057431Abstract: A method of manufacturing a semiconductor device includes forming a stacked structure including trenches having different depths, forming an insulating layer on the stacked structure to fill the trenches, and forming a plurality of protrusions located corresponding to locations of the trenches by patterning the insulating layer. The method also includes forming insulating patterns filling the trenches, respectively, by planarizing the patterned insulating layer including the plurality of protrusions.Type: ApplicationFiled: April 16, 2020Publication date: February 25, 2021Applicant: SK hynix Inc.Inventors: Byung Woo KANG, Sae Jun KWON, Hwal Pyo KIM, Jin Taek PARK, Yang Seok LIM, Young Ock HONG
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Publication number: 20200381447Abstract: The present technology provides a semiconductor memory device. The semiconductor memory device includes a source film spaced from a substrate and disposed on the substrate, a conductive contact plug penetrating the source film, and a dummy stack body including dummy interlayer insulating films and sacrificial insulating films alternately stacked on the conductive contact plug.Type: ApplicationFiled: October 31, 2019Publication date: December 3, 2020Applicant: SK hynix Inc.Inventors: Jae Taek KIM, Young Ock HONG
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Patent number: 10566343Abstract: A semiconductor memory device mc des a substrate defined with cell regions and a contact region between the cell regions; a dielectric structure formed over the contact region; a memory block having cell parts which are respectively formed over the cell regions, a coupling part which is formed over the contact region and couples the cell parts, and a through part which accommodates the dielectric structure; a peripheral circuit formed over the substrate under the memory block; bottom wiring lines disposed between the memory block and the peripheral circuit, and electrically coupled with the peripheral circuit; top wiring lines disposed over the memory block; and contact plugs passing through the dielectric structure and coupling the bottom wiring lines and the top wiring lines.Type: GrantFiled: November 3, 2017Date of Patent: February 18, 2020Assignee: SK hynix Inc.Inventors: Sung-Lae Oh, Jin-Ho Kim, Chang-Man Son, Go-Hyun Lee, Young-Ock Hong
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Publication number: 20180053782Abstract: A semiconductor memory device mc des a substrate defined with cell regions and a contact region between the cell regions; a dielectric structure formed over the contact region; a memory block having cell parts which are respectively formed over the cell regions, a coupling part which is formed over the contact region and couples the cell parts, and a through part which accommodates the dielectric structure; a peripheral circuit formed over the substrate under the memory block; bottom wiring lines disposed between the memory block and the peripheral circuit, and electrically coupled with the peripheral circuit; top wiring lines disposed over the memory block; and contact plugs passing through the dielectric structure and coupling the bottom wiring lines and the top wiring lines.Type: ApplicationFiled: November 3, 2017Publication date: February 22, 2018Inventors: Sung-Lae OH, Jin-Ho KIM, Chang-Man SON, Go-Hyun LEE, Young-Ock HONG
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Patent number: 9837433Abstract: A semiconductor memory device includes a substrate defined with cell regions and a contact region between the cell regions; a dielectric structure formed over the contact region; a memory block having cell parts which are respectively formed over the cell regions, a coupling part which is formed over the contact region and couples the cell parts, and a through part which accommodates the dielectric structure; a peripheral circuit formed over the substrate under the memory block; bottom wiring lines disposed between the memory block and the peripheral circuit, and electrically coupled with the peripheral circuit; top wiring lines disposed over the memory block; and contact plugs passing through the dielectric structure and coupling the bottom wiring lines and the top wiring lines.Type: GrantFiled: September 8, 2016Date of Patent: December 5, 2017Assignee: SK Hynix Inc.Inventors: Sung-Lae Oh, Jin-Ho Kim, Chang-Man Son, Go-Hyun Lee, Young-Ock Hong
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Publication number: 20170323898Abstract: A semiconductor memory device includes a substrate defined with cell regions and a contact region between the cell regions; a dielectric structure formed over the contact region; a memory block having cell parts which are respectively formed over the cell regions, a coupling part which is formed over the contact region and couples the cell parts, and a through part which accommodates the dielectric structure; a peripheral circuit formed over the substrate under the memory block; bottom wiring lines disposed between the memory block and the peripheral circuit, and electrically coupled with the peripheral circuit; top wiring lines disposed over the memory block; and contact plugs passing through the dielectric structure and coupling the bottom wiring lines and the top wiring lines.Type: ApplicationFiled: September 8, 2016Publication date: November 9, 2017Inventors: Sung-Lae OH, Jin-Ho KIM, Chang-Man SON, Go-Hyun LEE, Young-Ock HONG