Patents by Inventor Young Ok Hong
Young Ok Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150263011Abstract: A semiconductor device and a method of manufacturing the same, wherein the semiconductor device includes a memory string; a first metal pattern for a source line formed under the memory string; a second metal pattern for a peripheral circuit interconnection horizontally spaced apart from the first metal pattern; and peripheral circuit transistors connected to the second metal pattern.Type: ApplicationFiled: September 8, 2014Publication date: September 17, 2015Inventor: Young Ok HONG
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Patent number: 9000510Abstract: A nonvolatile memory device includes: a channel layer extending in a vertical direction from a substrate; a plurality of interlayer dielectric layers and word lines alternately stacked along the channel layer over the substrate; a bit line formed under plurality of interlayer dielectric layers and word lines, coupled to the channel layer, and extending in a direction crossing the word lines; and a common source layer coupled to the channel layer and formed over the plurality of interlayer dielectric layers and word lines.Type: GrantFiled: September 10, 2012Date of Patent: April 7, 2015Assignee: SK Hynix Inc.Inventor: Young-Ok Hong
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Patent number: 8754395Abstract: Disclosed is a semiconductor device and a method of manufacturing the same. The semiconductor device includes first material layers and second material layers alternately stacked on a first conductive layer. Through holes, each through holes including a first through region, second through region and trench, wherein the first and second through regions pass through the first and second material layers, and the trench is formed in the first conductive layer to connect the first through region and the second through region. Resistive layers, each resistive layer including a first region are disposed in the first through region, a second region disposed in the second through region, and a third region disposed in the trench.Type: GrantFiled: March 14, 2013Date of Patent: June 17, 2014Assignee: SK Hynix Inc.Inventors: Young Ok Hong, Kyoung A Kim
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Publication number: 20140151627Abstract: Disclosed is a semiconductor device and a method of manufacturing the same. The semiconductor device includes first material layers and second material layers alternately stacked on a first conductive layer. Through holes, each through holes including a first through region, second through region and trench, wherein the first and second through regions pass through the first and second material layers, and the trench is formed in the first conductive layer to connect the first through region and the second through region. Resistive layers, each resistive layer including a first region are disposed in the first through region, a second region disposed in the second through region, and a third region disposed in the trench.Type: ApplicationFiled: March 14, 2013Publication date: June 5, 2014Applicant: SK HYNIX INC.Inventors: Young Ok HONG, Kyoung A KIM
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Publication number: 20130168757Abstract: A nonvolatile memory device includes a channel layer extending in a vertical direction from a substrate, a plurality of interlayer dielectric layers and word lines alternately stacked along the channel layer over the substrate; a bit line formed under plurality of interlayer dielectric layers and word lines, coupled to the channel layer, and extending in a direction crossing the word lines, and a common source layer coupled to the channel layer and formed over the plurality of interlayer dielectric layers and word lines.Type: ApplicationFiled: September 10, 2012Publication date: July 4, 2013Inventor: Young-Ok HONG
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Patent number: 8377782Abstract: A method for fabricating a non-volatile memory device with asymmetric source/drain junctions, wherein a gate stack is formed on a semiconductor substrate, and impurity ions are implanted at a predetermined angle to form a source/drain junction in the semiconductor substrate. Thermal treatment of the semiconductor substrate forms an asymmetrically disposed source/drain junction between adjacent gate stacks.Type: GrantFiled: December 27, 2011Date of Patent: February 19, 2013Assignee: Hynix Semiconductor Inc.Inventors: Young Ok Hong, Myung Shik Lee
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Patent number: 8338874Abstract: A flash memory device includes a substrate; a cell stack having a semiconductor layer for providing junction areas and channel areas and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked; an array of gate columns, the gate columns penetrating through the cell stack, perpendicular to the substrate; and a trap layered stack introduced into an interface between the gate columns and the cell stack to store charge.Type: GrantFiled: May 11, 2012Date of Patent: December 25, 2012Assignee: Hynix Semiconductor Inc.Inventors: Hack Seob Shin, Kyoung Hwan Park, Young Ok Hong, Yu Jin Park
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Publication number: 20120217572Abstract: A flash memory device includes a substrate; a cell stack having a semiconductor layer for providing junction areas and channel areas and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked; an array of gate columns, the gate columns penetrating through the cell stack, perpendicular to the substrate; and a trap layered stack introduced into an interface between the gate columns and the cell stack to store charge.Type: ApplicationFiled: May 11, 2012Publication date: August 30, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Hack Seob Shin, Kyoung Hwan Park, Young Ok Hong, Yu Jin Park
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Publication number: 20120168858Abstract: A method of fabricating a non-volatile memory device includes providing a substrate with a cell region where a plurality of memory cells that are stacked vertically are to be formed and a peripheral circuit region where a peripheral circuit device is to be formed. Forming a gate structure where an inter-layer dielectric layer and a gate electrode layer are alternately stacked over the substrate of the cell region and the peripheral circuit region. Forming a first trench that isolates the gate electrode layers in one direction by selectively etching the gate structure of the cell region and forming a trench by selectively etching the gate structure corresponding to a contact formation region of the peripheral circuit region.Type: ApplicationFiled: September 23, 2011Publication date: July 5, 2012Applicant: Hynix Semiconductor Inc.Inventor: Young-Ok HONG
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Patent number: 8203177Abstract: A flash memory device includes a substrate; a cell stack having a semiconductor layer for providing junction areas and channel areas and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked; an array of gate columns, the gate columns penetrating through the cell stack, perpendicular to the substrate; and a trap layered stack introduced into an interface between the gate columns and the cell stack to store charge.Type: GrantFiled: August 17, 2010Date of Patent: June 19, 2012Assignee: Hynix Semiconductor Inc.Inventors: Hack Seob Shin, Kyoung Hwan Park, Young Ok Hong, Yu Jin Park
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Publication number: 20120094451Abstract: A method for fabricating a non-volatile memory device with asymmetric source/drain junctions, wherein a gate stack is formed on a semiconductor substrate, and impurity ions are implanted at a predetermined angle to form a source/drain junction in the semiconductor substrate. Thermal treatment of the semiconductor substrate forms an asymmetrically disposed source/drain junction between adjacent gate stacks.Type: ApplicationFiled: December 27, 2011Publication date: April 19, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Young Ok HONG, Myung Shik LEE
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Patent number: 8110866Abstract: Disclosed herein are non-volatile memory devices with asymmetric source/drain junctions and a method for fabricating the same. According to the method, a gate stack is formed on a semiconductor substrate, and impurity ions are implanted at a predetermined angle to form a source/drain junction in the semiconductor substrate. Thermal treatment of the semiconductor substrate forms an asymmetrically disposed source/drain junction between adjacent gate stacks.Type: GrantFiled: June 3, 2008Date of Patent: February 7, 2012Assignee: Hynix Semiconductor Inc.Inventors: Young Ok Hong, Myung Shik Lee
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Publication number: 20110204430Abstract: A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.Type: ApplicationFiled: April 29, 2011Publication date: August 25, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Se Jun KIM, Eun Seok CHOI, Kyoung Hwan PARK, Hyun Seung YOO, Myung Shik LEE, Young Ok HONG, Jung Ryul AHN, Yong Top KIM, Kyung Pil HWANG, Won Sic WOO, Jae Young PARK, Ki Hong LEE, Ki Seon PARK, Moon Sig JOO
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Patent number: 7955960Abstract: A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.Type: GrantFiled: March 21, 2008Date of Patent: June 7, 2011Assignee: Hynix Semiconductor Inc.Inventors: Se Jun Kim, Eun Seok Choi, Kyoung Hwan Park, Hyun Seung Yoo, Myung Shik Lee, Young Ok Hong, Jung Ryul Ahn, Yong Top Kim, Kyung Pil Hwang, Won Sic Woo, Jae Young Park, Ki Hong Lee, Ki Seon Park, Moon Sig Joo
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Manufacturing method of flash memory device comprising gate columns penetrating through a cell stack
Patent number: 7867831Abstract: A flash memory device includes a substrate, a cell stack having a semiconductor layer, in which junction areas for setting areas therebetween to channel areas are formed in a shape of a stripe, and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked. The flash memory device further includes an array of gate columns penetrating through the cell stack, perpendicular to the substrate and cutting through the junction areas to dispose the junction areas at both sides thereof, and a trap layered stack introduced into an interface between the gate column and the cell stack to store charge.Type: GrantFiled: September 18, 2008Date of Patent: January 11, 2011Assignee: Hynix Semiconductor Inc.Inventors: Hack Seob Shin, Kyoung Hwan Park, Young Ok Hong, Yu Jin Park -
Patent number: 7851847Abstract: A flash memory device includes a tunnel insulating layer formed over a semiconductor substrate, a charge trap layer formed over the tunnel insulating layer and configured to trap electric charges, a blocking insulating layer formed over the charge trap layer, and a gate electrode formed over the blocking insulating layer and including a first conductive layer and a second conductive layer doped with N and P impurities respectively. Further, a method of erasing a flash memory device includes providing a flash memory device including a gate electrode having a first conductive layer and a second conductive layer doped with N and P impurities respectively, and performing an erase operation in a state where a thickness of a depletion layer at an interface of a PN junction comprising the first conductive layer and the second conductive layer is increased due to a negative potential bias applied to the gate electrode.Type: GrantFiled: May 14, 2007Date of Patent: December 14, 2010Assignee: Hynix Semiconductor Inc.Inventor: Young-Ok Hong
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Publication number: 20100308398Abstract: A flash memory device includes a substrate; a cell stack having a semiconductor layer for providing junction areas and channel areas and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked; an array of gate columns, the gate columns penetrating through the cell stack, perpendicular to the substrate; and a trap layered stack introduced into an interface between the gate columns and the cell stack to store charge.Type: ApplicationFiled: August 17, 2010Publication date: December 9, 2010Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Hack Seob Shin, Kyoung Hwan Park, Young Ok Hong, Yu Jin Park
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Manufacturing method of flash memory device comprising gate columns penetrating through a cell stack
Patent number: 7799616Abstract: A flash memory device includes a substrate, a cell stack having a semiconductor layer, in which junction areas for setting areas therebetween to channel areas are formed in a shape of a stripe, and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked. The flash memory device further includes an array of gate columns penetrating through the cell stack, perpendicular to the substrate and cutting through the junction areas to dispose the junction areas at both sides thereof, and a trap layered stack introduced into an interface between the gate column and the cell stack to store charge.Type: GrantFiled: September 18, 2008Date of Patent: September 21, 2010Assignee: Hynix Semiconductor Inc.Inventors: Hack Seob Shin, Kyoung Hwan Park, Young Ok Hong, Yu Jin Park -
Patent number: 7741717Abstract: A metal line of a semiconductor device comprising contact plugs, a plurality of first trenches, first metal lines, a plurality of second trenches, and second metal lines. The contact plugs are formed over a semiconductor substrate and are insulated from each other by a first insulating layer. The plurality of first trenches are formed in the first insulating layer and are connected to first contact plugs of the contact plugs. The first metal lines are formed within the first trenches and are connected to the first contact plugs. The plurality of second trenches are formed over the first metal lines and the first insulating layer and comprise a second insulating layer connected to second contact plugs of the contact plugs. The second metal lines are formed within the second trenches and are connected to the second contact plugs.Type: GrantFiled: June 29, 2007Date of Patent: June 22, 2010Assignee: Hynix Semiconductor, Inc.Inventors: Young Ok Hong, Dong Hwan Lee
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Publication number: 20090296476Abstract: A flash memory device includes a substrate, a cell stack having a semiconductor layer, in which junction areas for setting areas therebetween to channel areas are formed in a shape of a stripe, and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked. The flash memory device further includes an array of gate columns penetrating through the cell stack, perpendicular to the substrate and cutting through the junction areas to dispose the junction areas at both sides thereof, and a trap layered stack introduced into an interface between the gate column and the cell stack to store charge.Type: ApplicationFiled: September 18, 2008Publication date: December 3, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Hack Seob Shin, Kyoung Hwan Park, Young Ok Hong, Yu Jin Park