Patents by Inventor Young Ouk Kim

Young Ouk Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11496136
    Abstract: A clock generating circuit includes a first delay line, a second delay line, a selected phase mixing circuit and, a delay control circuit. The first delay line delays, based on a delay control signal, an input clock signal to generate a first delay clock signal. The second delay line delays, based on the delay control signal, the input clock signal to generate a second delay clock signal. The selected phase mixing circuit generates, based on a first selection signal and a second selection signal, an output clock signal from at least one between the first delay clock signal and the second delay clock signal. The delay control circuit monitors duty cycles of the first delay clock signal and the second delay clock signal to generate the first selection signal and the second selection signal thereby selecting at least one between the first delay line and the second delay line.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: November 8, 2022
    Assignee: SK hynix Inc.
    Inventors: Gyu Tae Park, Young Ouk Kim
  • Patent number: 11483004
    Abstract: A phase mixing circuit includes a first driver comprising 2n inverters configured to drive a first clock signal, where n is a positive integer, and a first selection circuit configured to couple each of the 2n inverters of the first driver to a first mixing node, on the basis of a weight having first to 2nth bits. The phase mixing circuit also includes a second driver comprising 2n inverters configured to drive a second clock signal and a second selection circuit configured to couple each of the 2n inverters of the second driver to the first mixing node, on the basis of an inverted signal of the weight.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: October 25, 2022
    Assignee: SK hynix Inc.
    Inventors: Gyu Tae Park, Young Ouk Kim
  • Publication number: 20220247390
    Abstract: A signal generation circuit includes a first delay circuit, a second delay circuit, and a duty control circuit. The first delay circuit delays a first input signal to generate a first output signal. The second delay circuit delays a second input signal to generate a second output signal. The duty control circuit compares phases of the first and second output signals and changes the value of the second delay control signal, and then decreases the times, by which the first and second input signals are delayed, by the same value.
    Type: Application
    Filed: April 21, 2022
    Publication date: August 4, 2022
    Applicant: SK hynix Inc.
    Inventors: Young Ouk KIM, Gyu Tae PARK
  • Patent number: 11349457
    Abstract: A signal generation circuit includes a first delay circuit, a second delay circuit, and a duty control circuit. The first delay circuit delays a first input signal to generate a first output signal. The second delay circuit delays a second input signal to generate a second output signal. The duty control circuit compares phases of the first and second output signals and changes the value of the second delay control signal, and then decreases the times, by which the first and second input signals are delayed, by the same value.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: May 31, 2022
    Assignee: SK hynix Inc.
    Inventors: Young Ouk Kim, Gyu Tae Park
  • Publication number: 20220123755
    Abstract: A phase mixing circuit includes a first driver comprising 2n inverters configured to drive a first clock signal, where n is a positive integer, and a first selection circuit configured to couple each of the 2n inverters of the first driver to a first mixing node, on the basis of a weight having first to 2nth bits. The phase mixing circuit also includes a second driver comprising 2n inverters configured to drive a second dock signal and a second selection circuit configured to couple each of the 2n inverters of the second driver to the first mixing node, on the basis of an inverted signal of the weight.
    Type: Application
    Filed: November 17, 2021
    Publication date: April 21, 2022
    Applicant: SK hynix Inc.
    Inventors: Gyu Tae PARK, Young Ouk KIM
  • Publication number: 20220094339
    Abstract: A signal generation circuit includes a first delay circuit, a second delay circuit, and a duty control circuit. The first delay circuit delays a first input signal to generate a first output signal. The second delay circuit delays a second input signal to generate a second output signal. The duty control circuit compares phases of the first and second output signals and changes the value of the second delay control signal, and then decreases the times, by which the first and second input signals are delayed, by the same value.
    Type: Application
    Filed: February 8, 2021
    Publication date: March 24, 2022
    Applicant: SK hynix Inc.
    Inventors: Young Ouk KIM, Gyu Tae PARK
  • Patent number: 11264994
    Abstract: A delay circuit includes a coarse delay circuit, a header circuit, and a phase mixing circuit. The coarse delay circuit is configured to delay a reference clock signal to generate a first clock signal and a second clock signal and to change each phase of the first clock signal and the second clock signal by double a unit phase. The header circuit is configured to receive the first clock signal and the second clock signal and to generate a first phase clock signal and a second phase clock signal, between which a phase difference corresponds to half of the unit phase. The phase mixing circuit is configured to mix phases of the first phase clock signal and the second phase clock signal to generate an output clock signal.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: March 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Young Ouk Kim
  • Patent number: 11050413
    Abstract: A latched comparator includes a first amplification circuit, a second amplification circuit and a latch circuit. The first amplification circuit changes voltage levels of first and second output nodes based on first and second input signals when an operation speed of a semiconductor apparatus is relatively slow. The second amplification circuit changes voltage levels of third and fourth output nodes based on the first and second input signals when the operation speed of the semiconductor apparatus is relatively fast. The latch circuit generates first and second latch signals based on the voltage levels of the first and second output nodes or based on the voltage levels of the third and fourth output nodes according to the operation speed of the semiconductor apparatus.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: June 29, 2021
    Assignee: SK hynix Inc.
    Inventors: Gyu Tae Park, Young Ouk Kim
  • Patent number: 11025255
    Abstract: A signal generation circuit includes a clock divider circuit, an off-pulse generation circuit, and an output signal generation circuit. The on-pulse generation circuit delays an input signal in synchronization with the first and second divided clock signals and generates an even on-pulse signal and an odd on-pulse signal. The off-pulse generation circuit delays the even on-pulse signal and the odd-on pulse signal in synchronization with the first divided clock signal and the second divided clock signal and generates a plurality of delay signals. The output signal generation circuit generates a first pre-output signal based on the delay signals delayed in synchronization with the first divided clock signal, generate a second pre-output signal based on the delay signals delayed in synchronization with the second divided clock signal, and generate an output signal based on the first and second pre-output signals.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: June 1, 2021
    Assignee: SK hynix Inc.
    Inventor: Young Ouk Kim
  • Publication number: 20210050855
    Abstract: A signal generation circuit includes a clock divider circuit, an off-pulse generation circuit, and an output signal generation circuit. The on-pulse generation circuit delays an input signal in synchronization with the first and second divided clock signals and generates an even on-pulse signal and an odd on-pulse signal. The off-pulse generation circuit delays the even on-pulse signal and the odd-on pulse signal in synchronization with the first divided clock signal and the second divided clock signal and generates a plurality of delay signals. The output signal generation circuit generates a first pre-output signal based on the delay signals delayed in synchronization with the first divided clock signal, generate a second pre-output signal based on the delay signals delayed in synchronization with the second divided clock signal, and generate an output signal based on the first and second pre-output signals.
    Type: Application
    Filed: March 5, 2020
    Publication date: February 18, 2021
    Applicant: SK hynix Inc.
    Inventor: Young Ouk KIM
  • Publication number: 20200266803
    Abstract: A latched comparator includes a first amplification circuit, a second amplification circuit and a latch circuit. The first amplification circuit changes voltage levels of first and second output nodes based on first and second input signals when an operation speed of a semiconductor apparatus is relatively slow. The second amplification circuit changes voltage levels of third and fourth output nodes based on the first and second input signals when the operation speed of the semiconductor apparatus is relatively fast. The latch circuit generates first and second latch signals based on the voltage levels of the first and second output nodes or based on the voltage levels of the third and fourth output nodes according to the operation speed of the semiconductor apparatus.
    Type: Application
    Filed: September 3, 2019
    Publication date: August 20, 2020
    Applicant: SK hynix Inc.
    Inventors: Gyu Tae PARK, Young Ouk KIM
  • Publication number: 20200111273
    Abstract: A system for diagnosing a grade of a used car according to an embodiment of the present invention includes: collecting basic information of a used car by using a module, and transmitting the same to a server; transmitting grade information of the used car to the server; securing big data within a database; securing an inference engine within the server by using enhanced learning information obtained by performing enhanced learning of relation between the basic information and a grade of the used car by using artificial intelligence; and collecting basic information of a used car to be diagnosed and transmitting the same to the server, and diagnosing a grade of the used car to be diagnosed based on the basic information of the used car to be diagnosed by using the inference engine.
    Type: Application
    Filed: August 21, 2018
    Publication date: April 9, 2020
    Inventors: Young Ouk KIM, Ha Gyeong SUNG, Hyung Su LEE, Se Woong JUN, Dong In SHIN
  • Patent number: 10152116
    Abstract: Systems and devices for recording and reproducing senses. One or more of touch sensations and smell sensations are received to produce at least one of touch input signals and smell input signals. The input signals are stored and processed, and at least one output signal can be produced. One or more of a touch output and a smell output can be generated. The touch input, the smell input, or both can be integrated with one or more of sight input and sound input.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: December 11, 2018
    Assignee: The Regents of the University of California
    Inventors: Deli Wang, Siarhei Vishniakou, Brian Wellington Lewis, Truong Nguyen, Young Ouk Kim, Wonha Kim
  • Publication number: 20150220199
    Abstract: Systems and devices for recording and reproducing senses. One or more of touch sensations and smell sensations are received to produce at least one of touch input signals and smell input signals. The input signals are stored and processed, and at least one output signal can be produced. One or more of a touch output and a smell output can be generated. The touch input, the smell input, or both can be integrated with one or more of sight input and sound input.
    Type: Application
    Filed: April 26, 2012
    Publication date: August 6, 2015
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Deli Wang, Siarhei Vishniakou, Brain Wellington Lewis, Truong Nguyen, Young Ouk Kim, Wonha Kim
  • Patent number: 8782617
    Abstract: Provided are an apparatus and method for OpenVG API translation, a mobile terminal comprising the translation apparatus, and a record medium storing the translation program. The apparatus comprises a data parsing unit, an OpenVG API script creating unit, and a raster image data output unit. The data parsing unit parses SVG format data depending on a data attribute. The OpenVG API script creating unit extracts an OpenVG API format syntax and creates an OpenVG API script. The raster image data output unit creates and outputs raster image data associated with the created OpenVG API script.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: July 15, 2014
    Assignee: Core Logic Inc.
    Inventor: Young Ouk Kim
  • Publication number: 20100045683
    Abstract: Techniques, apparatus and system are described for providing a hardware-type vector graphics acceleration. In one aspect, a hardware-type vector graphics accelerator includes graphics processing modules to communicate with a controller unit. The graphics processing modules include at least one of a rasterizing setup module, a scissor module, a paint generation module, an alpha masking module, and a blending module connected together according to a pipeline architecture to perform two-dimensional (2D) vector graphics acceleration in response to one or more commands received from the controller unit.
    Type: Application
    Filed: April 21, 2009
    Publication date: February 25, 2010
    Inventors: YOUNG OUK KIM, HYUN JAE WOO, CHAY HYUN KIM
  • Publication number: 20090273604
    Abstract: Techniques, apparatus, and system are described for providing a vector graphics processor. In one aspect, a vector graphics processor includes a preprocessing unit configured to generate a vector graphics element for vector graphics processing in response to receiving element data parsed from content included in an application. The vector graphics processor includes a converter to communicate with the preprocessing unit and configured to convert the generated vector graphics element into a vector graphics object. Also, the vector graphics processor includes a rendering unit to communicate with the converter and configured to render the vector graphics object by driving a vector graphics application programming interface (API).
    Type: Application
    Filed: April 17, 2009
    Publication date: November 5, 2009
    Inventor: Young Ouk Kim
  • Publication number: 20080134218
    Abstract: Provided are an apparatus and method for OpenVG API translation, a mobile terminal comprising the translation apparatus, and a record medium storing the translation program. The apparatus comprises a data parsing unit, an OpenVG API script creating unit, and a raster image data output unit. The data parsing unit parses SVG format data depending on a data attribute. The OpenVG API script creating unit extracts an OpenVG API format syntax and creates an OpenVG API script. The raster image data output unit creates and outputs raster image data associated with the created OpenVG API script.
    Type: Application
    Filed: August 22, 2007
    Publication date: June 5, 2008
    Inventor: Young Ouk Kim
  • Publication number: 20080127062
    Abstract: Provided are a method for creating Open Vector Graphic (OpenVG) contents and a computer readable record medium storing instructions for executing a method for creating OpenVG contents. The method comprises providing an environment in which contents are written; creating an OpenVG Application Program Interface (API) syntax associated with the written contents; driving and checking the created OpenVG API syntax; creating a final OpenVG API script made up of the OpenVG API syntax; and storing contents objectified by the final OpenVG API script.
    Type: Application
    Filed: August 22, 2007
    Publication date: May 29, 2008
    Inventor: Young Ouk Kim