Abstract: Provided is a nitride semiconductor device including: a substrate having through via holes; first and second nitride semiconductor layers sequentially stacked on the substrate; drain electrodes and source electrodes provided on the second nitride semiconductor layer; and an insulating pattern provided on the second nitride semiconductor layer, the insulating pattern having upper via holes provided on the drain electrodes, wherein the through via holes are extended into the first and second nitride semiconductor layers and expose a bottom of each of the source electrodes.

Abstract: Provided is a method of manufacturing a nitride semiconductor device. The method includes forming a plurality of electrodes on a growth substrate on which first and second nitride semiconductor layers are sequentially stacked, forming upper metal layers on the plurality of electrodes respectively, removing the growth substrate to expose a lower surface of the first nitride semiconductor layer, and forming a third nitride semiconductor layer and a lower metal layer sequentially on the exposed lower surface of the first nitride semiconductor layer.

Abstract: Disclosed is a manufacturing method of a high electron mobility transistor. The method includes: forming a source electrode and a drain electrode on a substrate; forming a first insulating film having a first opening on an entire surface of the substrate, the first opening exposing a part of the substrate; forming a second insulating film having a second opening within the first opening, the second opening exposing a part of the substrate; forming a third insulating film having a third opening within the second opening, the third opening exposing a part of the substrate; etching a part of the first insulating film, the second insulating film and the third insulating film so as to expose the source electrode and the drain electrode; and forming a T-gate electrode on a support structure including the first insulating film, the second insulating film and the third insulating film.

Abstract: Provided are an electronic chip and a method of fabricating the same. The semiconductor chip may include a substrate, an active device integrated on the substrate, a lower interlayered insulating layer covering the resulting structure provided with the active device, a passive device provided on the lower interlayered insulating layer, an upper interlayered insulating layer covering the resulting structure provided with the passive device, and a ground electrode provided on the upper interlayered insulating layer. The upper interlayered insulating layer may be formed of a material, whose dielectric constant may be higher than that of the lower interlayered insulating layer.

Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.

Abstract: Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode; and a metal configured to connect the field plate and the source electrode.

Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.

Abstract: Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode; and a metal configured to connect the field plate and the source electrode.

Abstract: Provided are an electronic chip and a method of fabricating the same. The semiconductor chip may include a substrate, an active device integrated on the substrate, a lower interlayered insulating layer covering the resulting structure provided with the active device, a passive device provided on the lower interlayered insulating layer, an upper interlayered insulating layer covering the resulting structure provided with the passive device, and a ground electrode provided on the upper interlayered insulating layer. The upper interlayered insulating layer may be formed of a material, whose dielectric constant may be higher than that of the lower interlayered insulating layer.

Abstract: A method of manufacturing a semiconductor device includes forming devices including source, drain and gate electrodes on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked, etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode, conformally forming a ground interconnection on the back surface of the substrate having the via-hole, forming a protecting layer on the front surface of the substrate, and cutting the substrate to separate the devices from each other.

Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.

Abstract: A method for fabricating a field effect transistor according to an exemplary embodiment of the present disclosure includes: forming an active layer, a cap layer, an ohmic metal layer and an insulating layer on a substrate; forming multilayered photoresists on the insulating layer; patterning the multilayered photoresists to form a photoresist pattern including a first opening for gate electrode and a second opening for field electrode; etching the insulating layer by using the photoresist pattern as an etching mask so that the insulating layer in the first opening is etched more deeply and the cap layer is exposed through the first opening; etching the cap layer exposed by etching the insulating layer through the first opening to form a gate recess region; and depositing a metal on the gate recess region and the etched insulating layer to form a gate-field electrode layer.

Abstract: Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode; and a metal configured to connect the field plate and the source electrode.

Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.