Patents by Inventor Young-Seog Kang

Young-Seog Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8229205
    Abstract: A pattern matching method for use in manufacturing a semiconductor memory device increases a pattern matching rate between a GDS image and an SEM image. The pattern matching method includes extracting a scanning electron microscope (SEM) image and a graphic data system (GDS) image to perform a pattern matching; performing a two-dimensional Fourier transform (FFT) for the extracted GDS image and analyzing a low spatial frequency; deciding whether or not a pattern is a repeated pattern or non-repeated pattern by using the analyzed low spatial frequency; and limiting an X/Y range for a pattern matching when the decision result is for the repeated pattern, and then performing the pattern matching between the SEM image and the GDS image.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: July 24, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chan-Kyeong Hyon, Young-Seog Kang, Sang-Ho Lee, Hyun-Jong Lee
  • Patent number: 7900170
    Abstract: An optical proximity correction (OPC) system and methods thereof are provided. The example OPC system may include an integrated circuit (IC) layout generation unit generating an IC layout, a database unit storing a first plurality of OPC models, each of the first plurality of OPC models associated with one of a plurality of target specific characteristics and a mask layout generation unit including a model selector selecting a second plurality of OPC models based on a comparison between the target specific characteristics associated with the plurality of OPC models and the generated IC layout, the mask layout generation unit generating a mask layout based on the IC layout and the selected second plurality of OPC models.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: March 1, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Soo Suh, Young-Seog Kang, Han-Ku Cho, Sang-Gyun Woo
  • Publication number: 20090103799
    Abstract: A pattern matching method for use in manufacturing a semiconductor memory device increases a pattern matching rate between a GDS image and an SEM image. The pattern matching method includes extracting a scanning electron microscope (SEM) image and a graphic data system (GDS) image to perform a pattern matching; performing a two-dimensional furrier transform (FFT) for the extracted GDS image and analyzing a low spatial frequency; deciding whether or not a pattern is a repeated pattern or non-repeated pattern by using the analyzed low spatial frequency; and limiting an X/Y range for a pattern matching when the decision result is for the repeated pattern, and then performing the pattern matching between the SEM image and the GDS image.
    Type: Application
    Filed: October 17, 2008
    Publication date: April 23, 2009
    Inventors: Chan-Kyeong Hyon, Young-Seog Kang, Sang-Ho Lee, Hyun-Jong Lee
  • Patent number: 7475383
    Abstract: Provided is a method of fabricating a photo mask. The method includes preparing a model group including optical proximity correction (OPC) models and generating a preliminary mask layout using an integrated circuit (IC) layout. A contour image may be produced from the preliminary mask layout through a simulation using an optical model. Subsequently, the preliminary mask layout may be compared with the contour image and the comparison result may be analyzed to produce analysis data for providing criteria used in selecting an OPC model. An OPC model suitable for the preliminary mask layout may be selected from the model group based on the analysis data. An OPC process may be performed on the preliminary mask layout using the selected OPC model to generate a mask layout.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: January 6, 2009
    Assignee: Samsung Electronics Co. Ltd.
    Inventors: Sung-Soo Suh, Young-Seog Kang, In-Sung Kim
  • Publication number: 20080187211
    Abstract: A global matching method for semiconductor memory device fabrication may include extracting a graphic data system (GDS) image and a scanning electron microscope (SEM) image of patterns in a region on a wafer. First directional edges extending in a first direction and second directional edges extending in a second direction may be separately extracted from each of the GDS image and the SEM image with the first and second directions being different. The GDS image and the SEM image may be matched with respect to either the first directional edges or the second directional edges which are relatively shorter. After the relatively shorter edges of the GDS image and the SEM image are matched, the GDS image and the SEM image may be matched with respect to relatively longer edges, based on a result of the matching with respect to the relatively shorter edges, thereby completing pattern matching of the GDS image and the SEM image.
    Type: Application
    Filed: July 23, 2007
    Publication date: August 7, 2008
    Inventors: Chan-Kyeong Hyon, Young-Seog Kang, Sang-Ho Lee
  • Patent number: 7361433
    Abstract: A photomask includes a transparent substrate, and a plurality of light-shielding patterns repeatedly aligned on the transparent substrate in two dimensions. Each of the light-shielding patterns has length and width measurements that differ from each other. Further, the photomask includes at least one through hole penetrating a portion of each of the light-shielding patterns to expose the transparent substrate.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: April 22, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chan Hwang, In-Sung Kim, Young-Seog Kang
  • Publication number: 20080020297
    Abstract: A mask for photolithography with high exposure margin and a method of fabricating a photoresist pattern, using the mask are provided. The mask for photolithography includes a transparent substrate and a plurality of optical shielding members on the transparent substrate. Each optical shielding member includes a plurality of optical shielding layer segments which are separated from one another or which are connected to one another in their edges. The optical shielding member forms one image in which the optical shielding layer segments are connected to one another, upon photolithography.
    Type: Application
    Filed: May 11, 2007
    Publication date: January 24, 2008
    Inventors: Chang-hwan Kim, Young-cheol Lim, Young-seog Kang
  • Publication number: 20070162887
    Abstract: Provided is a method of fabricating a photo mask. The method includes preparing a model group including optical proximity correction (OPC) models and generating a preliminary mask layout using an integrated circuit (IC) layout. A contour image may be produced from the preliminary mask layout through a simulation using an optical model. Subsequently, the preliminary mask layout may be compared with the contour image and the comparison result may be analyzed to produce analysis data for providing criteria used in selecting an OPC model. An OPC model suitable for the preliminary mask layout may be selected from the model group based on the analysis data. An OPC process may be performed on the preliminary mask layout using the selected OPC model to generate a mask layout.
    Type: Application
    Filed: October 30, 2006
    Publication date: July 12, 2007
    Inventors: Sung-Soo Suh, Young-Seog Kang, In-Sung Kim
  • Publication number: 20070094635
    Abstract: An optical proximity correction (OPC) system and methods thereof are provided. The example OPC system may include an integrated circuit (IC) layout generation unit generating an IC layout, a database unit storing a first plurality of OPC models, each of the first plurality of OPC models associated with one of a plurality of target specific characteristics and a mask layout generation unit including a model selector selecting a second plurality of OPC models based on a comparison between the target specific characteristics associated with the plurality of OPC models and the generated IC layout, the mask layout generation unit generating a mask layout based on the IC layout and the selected second plurality of OPC models.
    Type: Application
    Filed: October 24, 2006
    Publication date: April 26, 2007
    Inventors: Sung-Soo Suh, Young-Seog Kang, Han-Ku Cho, Sang-Gyun Woo
  • Patent number: 7139064
    Abstract: In an optical system for forming a photoresist pattern on a substrate, an optical element such as a holographic optical element and an aperture plate provides an off-axis illumination beam having a hexapole. The photoresist pattern is formed to form structures such as contact pads, and includes first holes and second holes repeatedly arranged on the substrate. The hexapole includes four first poles symmetrically disposed with respect to an x-axis and a y-axis, and two second poles disposed in the x-axis so as to be symmetric with respect to the y-axis. The off-axis illumination beam may improve a resolution of the photoresist pattern and a depth of focus (DOF) of a light beam to be projected onto the substrate.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: November 21, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Seok Nam, Chan Hwang, Young-Seog Kang
  • Patent number: 6911286
    Abstract: A method of designing a phase grating pattern provides a modified form of illumination for a main mask, optimum for producing one or more target patterns on a wafer in a photolithographic process. Once the target pattern(s) to be formed on the wafer are decided, an area to be occupied by at least a portion of the phase grating is divided into a plurality of subcells, initial phase values are assigned to each of the subcells, and one of the subcells is randomly selected and the phase value last assigned thereto is changed, and the process is repeated. The process is in an iteration that changes the arrangement of the phase values assigned to the subcells until they converge on one which will provide the design for a phase grating which will produce a modified form of illumination optimum for use in forming the target pattern(s) on the wafer.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: June 28, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Seog Kang, Jong-Rak Park
  • Publication number: 20050105072
    Abstract: In an optical system for forming a photoresist pattern on a substrate, an optical element such as a holographic optical element and an aperture plate provides an off-axis illumination beam having a hexapole. The photoresist pattern is formed to form structures such as contact pads, and includes first holes and second holes repeatedly arranged on the substrate. The hexapole includes four first poles symmetrically disposed with respect to an x-axis and a y-axis, and two second poles disposed in the x-axis so as to be symmetric with respect to the y-axis. The off-axis illumination beam may improve a resolution of the photoresist pattern and a depth of focus (DOF) of a light beam to be projected onto the substrate.
    Type: Application
    Filed: June 14, 2004
    Publication date: May 19, 2005
    Inventors: Dong-Seok Nam, Chan Hwang, Young-Seog Kang
  • Publication number: 20050003278
    Abstract: A photomask includes a transparent substrate, and a plurality of light-shielding patterns repeatedly aligned on the transparent substrate in two dimensions. Each of the light-shielding patterns has length and width measurements that differ from each other. Further, the photomask includes at least one through hole penetrating a portion of each of the light-shielding patterns to expose the transparent substrate.
    Type: Application
    Filed: April 19, 2004
    Publication date: January 6, 2005
    Inventors: Chan Hwang, In-Sung Kim, Young-Seog Kang
  • Publication number: 20040013950
    Abstract: A method of designing a phase grating pattern provides a modified form of illumination for a main mask, optimum for producing one or more target patterns on a wafer in a photolithographic process. Once the target pattern(s) to be formed on the wafer are decided, an area to be occupied by at least a portion of the phase grating is divided into a plurality of subcells, initial phase values are assigned to each of the subcells, and one of the subcells is randomly selected and the phase value last assigned thereto is changed, and the process is repeated. The process is in an iteration that changes the arrangement of the phase values assigned to the subcells until they converge on one which will provide the design for a phase grating which will produce a modified form of illumination optimum for use in forming the target pattern(s) on the wafer.
    Type: Application
    Filed: April 9, 2003
    Publication date: January 22, 2004
    Inventors: Young-Seog Kang, Jong-Rak Park