Abstract: The present disclosure includes, in a dual polarized omni-directional antenna and a base station including the same, a plurality of radiating elements disposed to be spaced apart in one direction by the dual polarized omni-directional antenna, and a feed line for providing a feed signal to the plurality of radiating elements, and the plurality of radiating elements include a first radiator for generating one polarization of dual polarization, and a second radiator for generating the other polarization of the dual polarization, respectively, the first radiator is prepared on a first surface, and the second radiator is prepared on a second surface, and a main lobe direction of the first radiator and a main lobe direction of the second radiator are different directions from each other.

Abstract: A vehicle braking control method is provided. When a driver intends to drive a vehicle after the delivery of the vehicle or a factory mechanic intends to test the vehicle before the delivery of the vehicle after the engine is turned on even when a warning light is turned on due to the insufficiency of the brake fluid, a warning signal indicating that a level sensor is malfunctioning is generated using an instrument cluster, or driving torque of the engine is limited while a warning phrase indicating the insufficiency of the brake fluid is displayed using the cluster. Therefore, the vehicle may travel at a minimum speed. Thus, the driver is enabled to drive the vehicle to a safe place. Accordingly, a secondary accident is prevented and a subsequent maintenance operation is easily performed.

Abstract: A vehicle braking control method is provided. When a driver intends to drive a vehicle after the delivery of the vehicle or a factory mechanic intends to test the vehicle before the delivery of the vehicle after the engine is turned on even when a warning light is turned on due to the insufficiency of the brake fluid, a warning signal indicating that a level sensor is malfunctioning is generated using an instrument cluster, or driving torque of the engine is limited while a warning phrase indicating the insufficiency of the brake fluid is displayed using the cluster. Therefore, the vehicle may travel at a minimum speed. Thus, the driver is enabled to drive the vehicle to a safe place. Accordingly, a secondary accident is prevented and a subsequent maintenance operation is easily performed.

Abstract: A memory device includes: memory cells arranged in rows and columns; and regulated ground circuits corresponding to the columns. Each regulated ground circuit includes: a column ground node; at least three low-side voltage sources; at least three switches, each of the at least three switches being coupled between the column ground node and a corresponding one of the at least three voltage sources; and each of the at least three switches being controlled by a corresponding one of different control signals; Each memory cell includes: a high-side voltage source; an internal ground node coupled to the column ground node; and a cross latch having output and output_bar nodes. The cross latch is coupled between the high-side voltage source and the internal ground node, and is configured to selectively connect the output and output_bar nodes to corresponding bit and bit_bar lines.

Abstract: A memory device includes: memory cells arranged in rows and columns; and regulated ground circuits corresponding to the columns. Each regulated ground circuit includes: a column ground node; at least three low-side voltage sources; at least three switches, each of the at least three switches being coupled between the column ground node and a corresponding one of the at least three voltage sources; and each of the at least three switches being controlled by a corresponding one of different control signals; Each memory cell includes: a high-side voltage source; an internal ground node coupled to the column ground node; and a cross latch having output and output_bar nodes. The cross latch is coupled between the high-side voltage source and the internal ground node, and is configured to selectively connect the output and output_bar nodes to corresponding bit and bit_bar lines.

Abstract: A method of writing data to an accessed memory cell of an accessed column of an accessed section of a memory array includes, electrically coupling a first voltage source of at least three voltage sources to a column internal ground node of the accessed column; and electrically coupling the first voltage source of the at least three voltage sources to a column internal ground node of an un-accessed column of an un-accessed segment. The memory array has at least one segment. Each memory cell has an internal ground node. The at least one segment has at least one section, and each section has at least one column and at least one row. Each column has at least three switches and a column internal ground node capable of being electrically coupled to at least three voltage sources through a corresponding one of the at least three switches.

Abstract: A method of writing data to an accessed memory cell of an accessed column of an accessed section of a memory array includes, electrically coupling a first voltage source of at least three voltage sources to a column internal ground node of the accessed column; and electrically coupling the first voltage source of the at least three voltage sources to a column internal ground node of an un-accessed column of an un-accessed segment. The memory array has at least one segment. Each memory cell has an internal ground node. The at least one segment has at least one section, and each section has at least one column and at least one row. Each column has at least three switches and a column internal ground node capable of being electrically coupled to at least three voltage sources through a corresponding one of the at least three switches.

Abstract: A method of designing a content-addressable memory (CAM) includes associating CAM cells with a summary circuit. The summary circuit includes a first level of logic gates and a second level of logic gates. The first level of logic gates have inputs each configured to receive an output of a corresponding one of the plurality of CAM cell. The second level of logic gates have inputs each configured to receive an output of a corresponding one of the first level of logic gates. Logic gates in at least one of the first level of logic gates or the second level of logic gates are selected to have an odd number of input pins so that an input pin and an output pin share a layout sub-slot.

Abstract: A method includes causing, by a first circuit, a first signal transition at a first node based on a clock signal. A first edge, from a first level to a second level, of a word line signal is generated responsive to the first signal transition. A second signal transition at a second node is caused by a second circuit based on the clock signal. The second circuit and the first circuit are configured to cause the second signal transition to occur later than the first signal transition by a delay time. A first edge, from a third logic level to a fourth level, of a tracking word line signal is generated responsive to the second signal transition.

Abstract: A method of reading data from an accessed memory cell of an accessed column of an accessed section of a memory array includes, in the accessed section, electrically coupling a first voltage source of at least three voltage sources to a corresponding column internal ground node of the accessed column; and electrically coupling the first voltage source to a corresponding column internal ground node of an un-accessed column. The memory array has at least one segment, the at least one segment has at least one section, and each section has at least one column. Each column has at least three switches and a column internal ground node capable of being electrically coupled to at least three voltage sources through a corresponding one of the at least three switches.

Abstract: A circuit including a memory circuit, the memory circuit includes a first plurality of memory arrays and a first plurality of keepers, each keeper of the first plurality of keepers is electrically coupled with a corresponding one of the first plurality of memory arrays. The memory circuit further includes a first current limiter electrically coupled with and shared by the first plurality of keepers.

Abstract: A method of designing a content-addressable memory (CAM) includes associating CAM cells with a summary circuit. The summary circuit includes a first level of logic gates and a second level of logic gates. The first level of logic gates have inputs each configured to receive an output of a corresponding one of the plurality of CAM cell. The second level of logic gates have inputs each configured to receive an output of a corresponding one of the first level of logic gates. Logic gates in at least one of the first level of logic gates or the second level of logic gates are selected to have an odd number of input pins so that an input pin and an output pin share a layout sub-slot.

Abstract: A memory array comprises a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns includes a first voltage circuit coupled to internal first nodes of memory cells in the one of the plurality of columns and a second voltage circuit coupled to internal second nodes of the memory cells in the one of the plurality of columns. The first voltage circuit is configured to provide one of a first supply voltage and a second supply voltage lower than the first supply voltage to the internal first nodes. The second voltage circuit is configured to provide one of a first reference voltage and a second reference voltage higher than the first reference voltage to the internal second nodes.

Abstract: A memory includes a plurality of content-addressable memory (CAM) cells and a summary circuit associated with the plurality of CAM cells. The summary circuit includes a first level of logic gates and a second level of logic gates. The first level of logic gates have inputs each configured to receive an output of a corresponding one of the plurality of CAM cell. The second level of logic gates have inputs each configured to receive an output of a corresponding one of the first level of logic gates.

Abstract: A method includes causing, by a first circuit, a first signal transition at a first node based on a clock signal. A first edge, from a first level to a second level, of a word line signal is generated responsive to the first signal transition. A second signal transition at a second node is caused by a second circuit based on the clock signal. The second circuit and the first circuit are configured to cause the second signal transition to occur later than the first signal transition by a delay time. A first edge, from a third logic level to a fourth level, of a tracking word line signal is generated responsive to the second signal transition.

Abstract: A circuit includes a word line driver for driving a world line and a tracking word line driver for driving a tracking word line. The pulse width of a world line signal on the world line is driven to be larger than that of a tracking world line signal on the tracking world line to assist writing under difficult conditions. Because the tracking word line signal is activated later than the word line signal being activated but is deactivated at the same time with the word line, the pulse width of the word line signal is larger.

Abstract: A method of reading data from an accessed memory cell of an accessed column of an accessed section of a memory array includes, in the accessed section, electrically coupling a first voltage source of at least three voltage sources to a corresponding column internal ground node of the accessed column; and electrically coupling the first voltage source to a corresponding column internal ground node of an un-accessed column. The memory array has at least one segment, the at least one segment has at least one section, and each section has at least one column. Each column has at least three switches and a column internal ground node capable of being electrically coupled to at least three voltage sources through a corresponding one of the at least three switches.

Abstract: A time delay is determined to cover a timing of a memory cell in a memory macro having a tracking circuit. Based on the time delay, a capacitance corresponding to the time delay is determined. A capacitor having the determined capacitance is utilized. The capacitor is coupled to a first data line of a tracking cell of the tracking circuit. A first transition of the first data line causes a first transition of a second data line of the memory cell.

Abstract: A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised.

Abstract: Some embodiments regard a memory array comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns; wherein a column of the plurality of columns includes a column ground node; at least two voltage sources configured to be selectively coupled to the column ground node; and a plurality of memory cells having a plurality of internal ground nodes electrically coupled together and to the column ground node.