Patents by Inventor YoungSeok Hong

YoungSeok Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240149314
    Abstract: Provided is a substrate processing apparatus configured to process a substrate having a notch including a plurality of rollers contacting a circumference of the substrate and configured to rotate the substrate, a first sensor configured to sense an impact between the plurality of rollers and the substrate, and a signal processing unit configured to detect revolutions per unit time of the substrate, based on a first sensing signal output by the first sensor.
    Type: Application
    Filed: June 25, 2023
    Publication date: May 9, 2024
    Inventors: Hyunwoo Noh, Kyoungwoo Kim, Youngseok Jung, Youngjin Hong, Soochan Oh, Sungwoo Shin, Namhoon Lee, Bongju Lee
  • Patent number: 11919080
    Abstract: The successful fabrication of alloy foam (or porous alloy) is very rare, despite their potentially better properties and wider applicability than pure metallic foams. The processing of three-dimensional copper-nickel alloy foams is achieved through a strategic solid-solution alloying method based on oxide powder reduction or sintering processes, or both. Solid-solution alloy foams with five different compositions are successfully created, resulting in open-pore structures with varied porosity. The corrosion resistance of the synthesized copper-nickel alloy foams is superior to those of the pure copper and nickel foams.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: March 5, 2024
    Assignee: CellMo Materials Innovation, Inc.
    Inventors: Kicheol Hong, Hyeji Park, Sukyung Lee, Youngseok Song, Gigap Han, Kyungju Nam, Heeman Choe
  • Patent number: 11800686
    Abstract: A solid state drive (SSD) apparatus includes a case including an air tunnel disposed between an inner plate and an upper wall and an accommodation space between the inner plate and a lower wall. The air tunnel extends in a first direction, and both end parts of the air tunnel are exposed to the outside. A substrate is disposed in the accommodation space. At least one semiconductor chip is disposed on the substrate.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: October 24, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungchul Hur, Jaehong Park, Bumjun Kim, Yusuf Cinar, Hanhong Lee, Youngseok Hong, Doil Kong, Jaeheon Ma
  • Publication number: 20220248569
    Abstract: A solid state drive (SSD) apparatus includes a case including an air tunnel disposed between an inner plate and an upper wall and an accommodation space between the inner plate and a lower wall. The air tunnel extends in a first direction, and both end parts of the air tunnel are exposed to the outside. A substrate is disposed in the accommodation space. At least one semiconductor chip is disposed on the substrate.
    Type: Application
    Filed: April 19, 2022
    Publication date: August 4, 2022
    Inventors: SUNGCHUL HUR, JAEHONG PARK, BUMJUN KIM, YUSUF CINAR, HANHONG LEE, YOUNGSEOK HONG, DOIL KONG, JAEHEON MA
  • Patent number: 11317540
    Abstract: A solid state drive (SSD) apparatus includes a case including an air tunnel disposed between an inner plate and an upper wall and an accommodation space between the inner plate and a lower wall. The air tunnel extends in a first direction, and both end parts of the air tunnel are exposed to the outside. A substrate is disposed in the accommodation space. At least one semiconductor chip is disposed on the substrate.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: April 26, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungchul Hur, Jaehong Park, Bumjun Kim, Yusuf Cinar, Hanhong Lee, Youngseok Hong, Doil Kong, Jaeheon Ma
  • Publication number: 20210092871
    Abstract: A solid state drive (SSD) apparatus includes a case including an air tunnel disposed between an inner plate and an upper wall and an accommodation space between the inner plate and a lower wall. The air tunnel extends in a first direction, and both end parts of the air tunnel are exposed to the outside. A substrate is disposed in the accommodation space. At least one semiconductor chip is disposed on the substrate.
    Type: Application
    Filed: August 5, 2020
    Publication date: March 25, 2021
    Inventors: SUNGCHUL HUR, JAEHONG PARK, BUMJUN KIM, YUSUF CINAR, HANHONG LEE, YOUNGSEOK HONG, DOIL KONG, JAEHEON MA
  • Patent number: 8611125
    Abstract: A packaged integrated circuit device includes a substrate, and a conductive pad and a chip stack on the substrate. A primary conductive line electrically connects the pad on the substrate to a conductive pad on one of the chips in the chip stack. Secondary conductive lines electrically connect the pad on the one of the chips to respective conductive pads on ones of the chips above and below the one of the chips in the chip stack. The primary conductive line may be configured to transmit a signal from the pad on the substrate to the pad on the one of the chips in the chip stack, and the secondary conductive lines may be configured to transmit the signal from the one of the chips to the ones of the chips thereabove and therebelow at a same time.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: December 17, 2013
    Assignee: Samsung Electroncis Co., Ltd.
    Inventor: YoungSeok Hong
  • Patent number: 8331121
    Abstract: A packaged integrated circuit device includes a substrate including a conductive pad thereon, and a chip stack including a plurality of chips on the substrate. A primary conductive line electrically connects the pad on the substrate to a conductive pad on one of the plurality of chips in the chip stack. Secondary conductive lines electrically connect the pad on the one of the plurality of chips to respective conductive pads on ones of the plurality of chips above and below the one of the plurality of chips in the chip stack. The primary conductive line may be configured to transmit a signal from the pad on the substrate to the pad on the one of the plurality of chips in the chip stack. After receiving the signal at the one of the plurality of chips, the secondary conductive lines may be configured to transmit the signal from the one of the plurality of chips to the ones of the plurality of chips above and below the one of the plurality of chips in the chip stack at a same time.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: December 11, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: YoungSeok Hong
  • Publication number: 20100265751
    Abstract: A packaged integrated circuit device includes a substrate including a conductive pad thereon, and a chip stack including a plurality of chips on the substrate. A primary conductive line electrically connects the pad on the substrate to a conductive pad on one of the plurality of chips in the chip stack. Secondary conductive lines electrically connect the pad on the one of the plurality of chips to respective conductive pads on ones of the plurality of chips above and below the one of the plurality of chips in the chip stack. The primary conductive line may be configured to transmit a signal from the pad on the substrate to the pad on the one of the plurality of chips in the chip stack. After receiving the signal at the one of the plurality of chips, the secondary conductive lines may be configured to transmit the signal from the one of the plurality of chips to the ones of the plurality of chips above and below the one of the plurality of chips in the chip stack at a same time.
    Type: Application
    Filed: February 23, 2010
    Publication date: October 21, 2010
    Inventor: YoungSeok Hong