Abstract: The present application relates to a method of generating a downlink frame. The method of generating the downlink frame includes: generating a first short sequence and a second short sequence indicating cell group information; generating a first scrambling sequence and a second scrambling sequence determined by the primary synchronization signal; generating a third scrambling sequence determined by the first short sequence and a fourth scrambling sequence determined by the second short sequence; scrambling the short sequences with the respective scrambling sequences; and mapping the secondary synchronization signal that includes the first short sequence scrambled with the first scrambling sequence, the second short sequence scrambled with the second scrambling sequence and the third scrambling sequence, the second short sequence scrambled with the first scrambling sequence and the first short sequence scrambled by the second scrambling sequence and the fourth scrambling sequence to a frequency domain.

Abstract: Provided is a data transmission system using a carrier aggregation. The data transmission system may assign a radio resource based on a correspondence relationship between a downlink and an uplink, and may transmit data using the assigned radio resource.

Abstract: A variable resistance semiconductor device includes a lower conductive wiring; a bottom electrode over the lower conductive wiring; a selection element pattern over the bottom electrode; a first intermediate electrode over the selection element pattern; a second intermediate electrode over the first intermediate electrode; a variable resistance element pattern over the second intermediate electrode; a top electrode over the variable resistance element pattern; and an upper conductive wiring over the top electrode. The first intermediate electrode includes a first material. The second intermediate electrode includes a second material which has a better oxidation resistance and a higher work function than the first material.

Abstract: A method for forming a semiconductor device is disclosed. The method for forming the semiconductor device includes forming a first sacrificial film over a target layer to be etched, forming a first partition mask over the first sacrificial film, forming a first sacrificial film pattern by etching the first sacrificial film using the first partition mask, forming a first spacer at a sidewall of the first sacrificial film pattern, and forming a first spacer pattern by removing the first sacrificial film pattern. The first partition mask includes a plurality of first line-shaped space patterns extending in a first direction. A width of at least one space pattern located at both edges from among the plurality of first space patterns is smaller than a width of each of other space patterns.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory comprises a first variable resistance element coupled between a first wiring and a second wiring, the first variable resistance element including a first variable resistance layer having a first width at a first distance from the first wiring; and a second variable resistance element coupled between the second wiring and a third wiring, the second variable resistance element including a second variable resistance layer having a second width at the first distance from the second wiring. The first width is greater than the second width.

Abstract: An electronic device may include a semiconductor memory. The semiconductor memory may include: row lines; column lines intersecting the row lines; memory cells located in intersection regions of the row lines and the column lines, the memory cells including upper and lower electrodes; and interface layers located between the lower electrodes of the memory cells and the row lines, the interface layers having a width narrower than that of the row lines.

Abstract: A method for forming a semiconductor device is disclosed. The method for forming the semiconductor device includes forming a first sacrificial film over a target layer to be etched, forming a first partition mask over the first sacrificial film, forming a first sacrificial film pattern by etching the first sacrificial film using the first partition mask, forming a first spacer at a sidewall of the first sacrificial film pattern, and forming a first spacer pattern by removing the first sacrificial film pattern. The first partition mask includes a plurality of first line-shaped space patterns extending in a first direction. A width of at least one space pattern located at both edges from among the plurality of first space patterns is smaller than a width of each of other space patterns.

Abstract: An electronic device may include a semiconductor memory. The semiconductor memory may include: row lines; column lines intersecting the row lines; memory cells located in intersection regions of the row lines and the column lines, the memory cells including upper and lower electrodes; and interface layers located between the lower electrodes of the memory cells and the row lines, the interface layers having a width narrower than that of the row lines.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory comprises a first variable resistance element coupled between a first wiring and a second wiring, the first variable resistance element including a first variable resistance layer having a first width at a first distance from the first wiring; and a second variable resistance element coupled between the second wiring and a third wiring, the second variable resistance element including a second variable resistance layer having a second width at the first distance from the second wiring. The first width is greater than the second width.

Abstract: A method for forming a semiconductor device is disclosed. The method for forming the semiconductor device includes forming a first sacrificial film over a target layer to be etched, forming a first partition mask over the first sacrificial film, forming a first sacrificial film pattern by etching the first sacrificial film using the first partition mask, forming a first spacer at a sidewall of the first sacrificial film pattern, and forming a first spacer pattern by removing the first sacrificial film pattern. The first partition mask includes a plurality of first line-shaped space patterns extending in a first direction. A width of at least one space pattern located at both edges from among the plurality of first space patterns is smaller than a width of each of other space patterns.

Abstract: A variable resistance semiconductor device includes a lower conductive wiring; a bottom electrode over the lower conductive wiring; a selection element pattern over the bottom electrode; a first intermediate electrode over the selection element pattern; a second intermediate electrode over the first intermediate electrode; a variable resistance element pattern over the second intermediate electrode; a top electrode over the variable resistance element pattern; and an upper conductive wiring over the top electrode. The first intermediate electrode includes a first material. The second intermediate electrode includes a second material which has a better oxidation resistance and a higher work function than the first material.

Abstract: A method for forming a semiconductor device is disclosed. The method for forming the semiconductor device includes forming a first sacrificial film over a target layer to be etched, forming a first partition mask over the first sacrificial film, forming a first sacrificial film pattern by etching the first sacrificial film using the first partition mask, forming a first spacer at a sidewall of the first sacrificial film pattern, and forming a first spacer pattern by removing the first sacrificial film pattern. The first partition mask includes a plurality of first line-shaped space patterns extending in a first direction. A width of at least one space pattern located at both edges from among the plurality of first space patterns is smaller than a width of each of other space patterns.

Abstract: In an embodiment, a substrate that includes a cell region and a dummy region is provided. Lower interconnection structures are formed in the cell region and the dummy region. One or more first multilayered structure patterns are formed in the cell region and one or more second multilayered structure patterns in the dummy region over the lower interconnection structures. The first multilayered structure patterns and second multilayered structure patterns extend in a first direction. Each of the second multilayered structure patterns includes an etch target layer. An insulating material layer is formed over the first multilayered structure patterns and the second multilayered structure patterns. An interlayer insulating layer that fills a space between two adjacent patterns of the first multilayered structure patterns and second multilayered structure patterns is formed by planarizing the insulating material layer. The etch target layer in each of the second multilayered structure patterns is removed.

Abstract: Semiconductor memory devices and electronic systems having the semiconductor memory devices are provided. One of the semiconductor memory device may include a plurality of first conductive interconnections extending in parallel in a first horizontal direction, a plurality of selection interconnections disposed on the first conductive interconnections, the selection interconnections extending in parallel in the first horizontal direction, a plurality of second conductive interconnections extending in parallel in a second horizontal direction that is perpendicular to the first horizontal direction, and a plurality of memory cell stacks respectively disposed in interconnection regions between the first conductive interconnections and the second conductive interconnections. Each of the memory cell stacks may include a variable resistive element.

Abstract: In an embodiment, a substrate that includes a cell region and a dummy region is provided. Lower interconnection structures are formed in the cell region and the dummy region. One or more first multilayered structure patterns are formed in the cell region and one or more second multilayered structure patterns in the dummy region over the lower interconnection structures. The first multilayered structure patterns and second multilayered structure patterns extend in a first direction. Each of the second multilayered structure patterns includes an etch target layer. An insulating material layer is formed over the first multilayered structure patterns and the second multilayered structure patterns. An interlayer insulating layer that fills a space between two adjacent patterns of the first multilayered structure patterns and second multilayered structure patterns is formed by planarizing the insulating material layer. The etch target layer in each of the second multilayered structure patterns is removed.

Abstract: A wireless power transmission apparatus includes a resonator configured to transmit power to another resonator, and a power supply unit configured to supply power to the resonator. The apparatus further includes a switching unit including a transistor configured to be turned on to connect the power supply unit to the resonator, and to be turned off to disconnect the power supply unit from the resonator, based on a control signal, and a diode connected in series to the transistor.

Abstract: An electronic device including a semiconductor memory unit that includes a cell structure having two memory cells, which share one selector, wherein the cell structure includes first electrodes, variable resistance patterns and second electrodes which are symmetrically disposed on both sides of the selector.

Abstract: An electronic device comprising a semiconductor memory unit that includes a cell structure having two memory cells, which share one selector, wherein the cell structure includes first electrodes, variable resistance patterns and second electrodes which are symmetrically disposed on both sides of the selector.

Abstract: A related content providing method using broadcast service guide information of a mobile terminal is disclosed. The method includes playing broadcast content stored in the mobile terminal, searching for real-time broadcast content related to the played broadcast content while displaying the played broadcast content, and displaying information associated with the searched real-time broadcast content.

Abstract: A wireless power transmission apparatus includes a resonator configured to transmit power to another resonator, and a power supply unit configured to supply power to the resonator. The apparatus further includes a switching unit including a transistor configured to be turned on to connect the power supply unit to the resonator, and to be turned off to disconnect the power supply unit from the resonator, based on a control signal, and a diode connected in series to the transistor.