Abstract: A display device comprises a substrate; a driving transistor including a first active layer and a switching transistor including a second active layer, the first active layer and the second active layer being disposed on the substrate; a first gate insulating layer disposed on the first active layer of the driving transistor and the second active layer of the switching transistor; first and second gate electrodes disposed on the first gate insulating layer to overlap the first active layer of the driving transistor and the second active layer of the switching transistor, respectively; a first interlayer insulating layer disposed on the first gate electrode and the second gate electrode; and a second interlayer insulating layer disposed on the first interlayer insulating layer to overlap the first active layer without overlapping the second active layer in a plan view.

Abstract: The present invention relates to a system for managing IFC versions by comparing two or more IFC files produced with a time interval therebetween so as to trace the alteration history, and to a method for managing the IFC file version thereof. A system for managing the IFC versions includes: a comparison target processing unit for acquiring first IFC file attribute information concerning a first IFC file and second IFC file attribute information concerning at least one second IFC file; a GUID comparison engine for comparing a first IFC file GUID set containing first IFC GUIDs with a second IFC file GUID set containing second IFC GUIDs; and a spatial object comparison engine for comparing a first IFC file spatial object information set containing first IFC file spatial objects with a second IFC file spatial object information set containing second IFC file spatial objects.

Abstract: The present invention relates to a system for managing IFC versions by comparing two or more IFC files produced with a time interval therebetween so as to trace the alteration history, and to a method for managing the IFC file version thereof. A system for managing the IFC versions includes: a comparison target processing unit for acquiring first IFC file attribute information concerning a first IFC file and second IFC file attribute information concerning at least one second IFC file; a GUID comparison engine for comparing a first IFC file GUID set containing first IFC GUIDs with a second IFC file GUID set containing second IFC GUIDs; and a spatial object comparison engine for comparing a first IFC file spatial object information set containing first IFC file spatial objects with a second IFC file spatial object information set containing second IFC file spatial objects.

Abstract: An organic light-emitting diode display driver adjusts the display scan period of the current driving the organic light-emitting diodes of a selected row based upon the sum of the display data corresponding to the selected row, thereby removing crosstalk in the OLED display panel. The driver includes an adder for adding the display data corresponding to the selected row and a scan period look-up table storing display scan period values. The scan period look-up table is configured such that it outputs display scan period values substantially proportional or inversely proportional to the sum of the display data to remove bright crosstalk or dark crosstalk, respectively, in the OLED display panel.

Abstract: Disclosed is an organic electro luminescence display driving circuit. According to the present invention, it is possible to prevent a generation of a row-line flashing, which may happen when a display signal from a display signal terminal enters the organic electro luminescence display driving circuit. The organic electro luminescence display driving circuit for shielding a row-line flashing according to the present invention includes a real display signal generating circuit, which is connected to a display signal terminal and a pre-signal terminal, for providing a bias circuit for column driving circuit and row-line bias circuit with a real display signal.

Abstract: A variable-length code decoding apparatus for decoding sequential variable-length codewords includes a first barrel shifter for producing a first window output sequence in response to a window control signal, a second barrel shifter for producing a second window output sequence and a code value in response to a decoded codeword length, a relay circuit for latching the second window output sequence for the clock cycle and providing the latched second window output sequence as a decoding output sequence, a first look-up table memory for producing the decoded codeword length in response to a pre.sub.-- fix code of the variable-length codeword that begins at the first bit position of the decoding output sequence, a second look-up table memory for producing a fixed-length word in response to the decoded codeword length and the code value, and an accumulation block for producing the window control signal.

Abstract: An efficient method and apparatus for decoding sequential variable-length codewords includes a first barrel shifter for producing a first window output sequence in response to a window control signal, a second barrel shifter for producing a second window output sequence and a code value in response to a decoded codeword length, a relay circuit for latching the second window output sequence for one-half the clock cycle and providing the latched second window output sequence as a decoding output sequence, a first look-up table memory for producing the decoded codeword length in response to a pre.sub.-- fix code of the variable-length codeword that begins at the first bit position of the decoding output sequence, a second look-up table memory for producing a fixed-length word in response to the decoded codeword length and the code value, and an accumulation block for producing the window control signal.

Abstract: A variable-length code decoding apparatus for decoding sequential variable-length codewords includes a first barrel shifter for producing a first window output sequence in response to a window control signal, a second barrel shifter for producing a second window output sequence and a code value in response to a decoded codeword length, a relay circuit for latching the second window output sequence for one-half the clock cycle and providing the latched second window output sequence as a decoding output sequence, a first look-up table memory for producing the decoded codeword length in response to a pre.sub.-- fix code of the variable-length codeword that begins at the first bit position of the decoding output sequence, a second look-up table memory for producing a fixed-length word in response to the decoded codeword length and the code value, and an accumulation block for producing the window control signal.

Abstract: A run-length decoding apparatus, for use in a video signal decoding system, for decoding a run level coded video signal to provide decoded video signal comprises an address generator, receiving the run data, for generating a write address denoting a memory location for storing the level data, a counter, responsive to a clock signal, for generating a read address for sequentially addressing the memory locations from an upper most memory location to a lower most memory location, and memory, having a number of memory locations, for storing the level data based on the write address, and for generating the decoded data stored in the memory locations based on the read addresses to thereby provide the decoded video signal.

Abstract: A variable-length code decoding apparatus for decoding sequential variable-length codewords includes a first barrel shifter for producing a first window output sequence in response to a window control signal, a second barrel shifter for producing a second window output sequence in response to a decoded codeword length, a relay circuit for latching the second window output sequence for one-half the clock cycle and providing the latched second window output sequence as a decoding output sequence, a first look-up table memory for producing the decoded codeword length and a pre.sub.-- fix code length in response to a pre.sub.-- fix code of the variable-length codeword that begins at the first bit position of the decoding output sequence, a third shifter for producing a code value in response to the pre.sub.