Patents by Inventor Young Seon You
Young Seon You has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240130255Abstract: The disclosure provides a structure and method for a memory element to confine a metal (e.g., a remaining portion of a metallic residue) with a spacer. A structure according to the disclosure includes a memory element over a first portion of an insulator layer. A portion of the memory element includes a sidewall over the insulator layer. A spacer is adjacent the sidewall of the memory element and on the first portion of the insulator layer. A metal-dielectric layer is within an interface between the spacer and the sidewall or an interface between the spacer and the first portion of the insulator layer. The insulator layer includes a second portion adjacent the first portion, and the second portion does not include the memory element, the spacer, and the metal-dielectric layer thereon.Type: ApplicationFiled: October 13, 2022Publication date: April 18, 2024Inventors: Robert Viktor Seidel, Suk Hee Jang, Anastasia Voronova, Young Seon You
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Patent number: 11594675Abstract: A memory device is provided, the memory device comprising a contact pillar in a dielectric layer. A magnetic tunnel junction may be provided over the contact pillar. A barrier layer may be provided on a sidewall of the magnetic tunnel junction and extending over a horizontal surface of the dielectric layer. A spacer may be provided over the barrier layer.Type: GrantFiled: June 4, 2020Date of Patent: February 28, 2023Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Suk Hee Jang, Funan Tan, Naganivetha Thiyagarajah, Young Seon You
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Publication number: 20210384416Abstract: A memory device is provided, the memory device comprising a contact pillar in a dielectric layer. A magnetic tunnel junction may be provided over the contact pillar. A barrier layer may be provided on a sidewall of the magnetic tunnel junction and extending over a horizontal surface of the dielectric layer. A spacer may be provided over the barrier layer.Type: ApplicationFiled: June 4, 2020Publication date: December 9, 2021Inventors: SUK HEE JANG, FUNAN TAN, NAGANIVETHA THIYAGARAJAH, YOUNG SEON YOU
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Patent number: 10608046Abstract: Devices and methods of forming a device. A two-terminal device element includes a device stack coupled between first and second terminals. The first terminal contacts a metal line in an underlying interconnect level, and the second terminal is formed over the device layer. An encapsulation liner covers exposed side surfaces of the device stack of the two-terminal device element. A dual damascene interconnect is coupled to the two-terminal device element.Type: GrantFiled: July 5, 2019Date of Patent: March 31, 2020Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Wanbing Yi, Curtis Chun-I Hsieh, Juan Boon Tan, Soh Yun Siah, Hai Cong, Alex See, Young Seon You, Danny Pak-Chum Shum, Hyunwoo Yang
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Publication number: 20190326352Abstract: Devices and methods of forming a device. A two-terminal device element includes a device stack coupled between first and second terminals. The first terminal contacts a metal line in an underlying interconnect level, and the second terminal is formed over the device layer. An encapsulation liner covers exposed side surfaces of the device stack of the two-terminal device element. A dual damascene interconnect is coupled to the two-terminal device element.Type: ApplicationFiled: July 5, 2019Publication date: October 24, 2019Inventors: Wanbing YI, Curtis Chun-I HSIEH, Juan Boon TAN, Soh Yun SIAH, Hai CONG, Alex SEE, Young Seon YOU, Danny Pak-Chum SHUM, Hyunwoo YANG
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Patent number: 10446607Abstract: Devices and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first and second regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the regions. A two-terminal device element which includes a device layer coupled in between first and second terminals is formed over the first upper dielectric layer in the second region. The first terminal contacts the metal line in the first upper interconnect level of the second region and the second terminal is formed on the device layer. An encapsulation liner covers at least exposed side surfaces of the device layer of the two-terminal device element. A dielectric layer which includes a second upper interconnect level with dual damascene interconnects is provided in the regions.Type: GrantFiled: December 28, 2016Date of Patent: October 15, 2019Assignee: GLOBALFOUNDARIES SINGAPORE PTE. LTD.Inventors: Wanbing Yi, Curtis Chun-I Hsieh, Juan Boon Tan, Soh Yun Siah, Hai Cong, Alex See, Young Seon You, Danny Pak-Chum Shum, Hyunwoo Yang
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Publication number: 20180182810Abstract: Devices and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first and second regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the regions. A two-terminal device element which includes a device layer coupled in between first and second terminals is formed over the first upper dielectric layer in the second region. The first terminal contacts the metal line in the first upper interconnect level of the second region and the second terminal is formed on the device layer. An encapsulation liner covers at least exposed side surfaces of the device layer of the two-terminal device element. A dielectric layer which includes a second upper interconnect level with dual damascene interconnects is provided in the regions.Type: ApplicationFiled: December 28, 2016Publication date: June 28, 2018Inventors: Wanbing YI, Curtis Chun-I HSIEH, Juan Boon TAN, Soh Yun SIAH, Hai CONG, Alex SEE, Young Seon YOU, Danny Pak-Chum SHUM, Hyunwoo YANG
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Patent number: 7705395Abstract: Disclosed is a flash memory cell and method of manufacturing the same, and programming/erasing/reading method thereof. The flash memory cell comprises a first tunnel oxide film formed at a given region of a semiconductor substrate, a first floating gate formed on the first tunnel oxide film, a second tunnel oxide film formed over the semiconductor substrate and along one sidewall of the first floating gate, a second floating gate isolated from the first floating gate while contacting the second tunnel oxide film, a dielectric film formed on the first floating gate and the second floating gate, a control gate formed on the dielectric film, a first junction region formed in the semiconductor substrate below one side of the second tunnel oxide film, and a second junction region formed in the semiconductor substrate below one side of the first tunnel oxide film. Therefore, the present invention can implement 2-bit cell or 3-bit cell of a high density using the existing process technology.Type: GrantFiled: October 8, 2008Date of Patent: April 27, 2010Assignee: Hynix Semiconductor Inc.Inventors: Sung Kee Park, Young Seon You, Yong Wook Kim, Yoo Nam Jeon
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Publication number: 20090026528Abstract: Disclosed is a flash memory cell and method of manufacturing the same, and programming/erasing/reading method thereof. The flash memory cell comprises a first tunnel oxide film formed at a given region of a semiconductor substrate, a first floating gate formed on the first tunnel oxide film, a second tunnel oxide film formed over the semiconductor substrate and along one sidewall of the first floating gate, a second floating gate isolated from the first floating gate while contacting the second tunnel oxide film, a dielectric film formed on the first floating gate and the second floating gate, a control gate formed on the dielectric film, a first junction region formed in the semiconductor substrate below one side of the second tunnel oxide film, and a second junction region formed in the semiconductor substrate below one side of the first tunnel oxide film. Therefore, the present invention can implement 2-bit cell or 3-bit cell of a high density using the existing process technology.Type: ApplicationFiled: October 8, 2008Publication date: January 29, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Sung Kee PARK, Young Seon YOU, Yong Wook KIM, Yoo Nam JEON
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Patent number: 6884679Abstract: Disclosed is a flash memory cell and method of manufacturing the same, and programming/erasing/reading method thereof. The flash memory cell comprises a first tunnel oxide film formed at a given region of a semiconductor substrate, a first floating gate formed on the first tunnel oxide film, a second tunnel oxide film formed over the semiconductor substrate and along one sidewall of the first floating gate, a second floating gate isolated from the first floating gate while contacting the second tunnel oxide film, a dielectric film formed on the first floating gate and the second floating gate, a control gate formed on the dielectric film, a first junction region formed in the semiconductor substrate below one side of the second tunnel oxide film, and a second junction region formed in the semiconductor substrate below one side of the first tunnel oxide film. Therefore, the present invention can implement 2-bit cell or 3-bit cell of a high density using the existing process technology.Type: GrantFiled: July 10, 2003Date of Patent: April 26, 2005Assignee: Hynix Semiconductor Inc.Inventors: Sung Kee Park, Young Seon You, Yong Wook Kim, Yoo Nam Jeon
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Patent number: 6734458Abstract: The present invention relates to a test pattern for measuring a contact resistance and method of manufacturing the same. In order to confirm that a contact resistance suitable for a semiconductor device before an actual process for manufacturing the device is performed, the present invention designs a test pattern for measuring the contact resistance depending on a design rule of a line contact actually applied to an actual device.Type: GrantFiled: December 28, 2001Date of Patent: May 11, 2004Assignee: Hynix Semiconductor Inc.Inventors: Ki Seog Kim, Young Seon You, Keun Woo Lee, Sung Kee Park
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Patent number: 6717848Abstract: The present invention relates to a sensing circuit in a multi-level flash memory cell capable of exactly sensing a state of the multi-level flash memory cell by sensing four states of the multi-level flash memory cell based on first through third reference cells. The first reference cell has a threshold voltage by which a program or erase state of a floating gate can be determined in a state that a capacitor of the multi-level flash memory cell is discharged, a second reference cell has a threshold voltage by which a charge or discharge state of the capacitor can be determined with the floating gate of the multi-level flash memory cell being at a discharge state, and a third reference cell has a threshold voltage by which a charge or discharge state of the capacitor can be determined with the floating gate of the multi-level flash memory cell being at a program state.Type: GrantFiled: November 5, 2002Date of Patent: April 6, 2004Assignee: Hynix Semiconductor Inc.Inventors: Ki Seog Kim, Young Seon You, Won Yeol Choi, Yoo Nam Jeon
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Publication number: 20040013001Abstract: Disclosed is a flash memory cell and method of manufacturing the same, and programming/erasing/reading method thereof. The flash memory cell comprises a first tunnel oxide film formed at a given region of a semiconductor substrate, a first floating gate formed on the first tunnel oxide film, a second tunnel oxide film formed over the semiconductor substrate and along one sidewall of the first floating gate, a second floating gate isolated from the first floating gate while contacting the second tunnel oxide film, a dielectric film formed on the first floating gate and the second floating gate, a control gate formed on the dielectric film, a first junction region formed in the semiconductor substrate below one side of the second tunnel oxide film, and a second junction region formed in the semiconductor substrate below one side of the first tunnel oxide film. Therefore, the present invention can implement 2-bit cell or 3-bit cell of a high density using the existing process technology.Type: ApplicationFiled: July 10, 2003Publication date: January 22, 2004Inventors: Sung Kee Park, Young Seon You, Yong Wook Kim, Yoo Nam Jeon
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Publication number: 20030123294Abstract: The present invention relates to a sensing circuit in a multi-level flash memory cell capable of exactly sensing a state of the multi-level flash memory cell by sensing four states of the multi-level flash memory cell based on first through third reference cells. The first reference cell has a threshold voltage by which a program or erase state of a floating gate can be determined in a state that a capacitor of the multi-level flash memory cell is discharged, a second reference cell has a threshold voltage by which a charge or discharge state of the capacitor can be determined with the floating gate of the multi-level flash memory cell being at a discharge state, and a third reference cell has a threshold voltage by which a charge or discharge state of the capacitor can be determined with the floating gate of the multi-level flash memory cell being at a program state.Type: ApplicationFiled: November 5, 2002Publication date: July 3, 2003Inventors: Ki Seog Kim, Young Seon You, Won Yeol Choi, Yoo Nam Jeon
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Publication number: 20030100134Abstract: The present invention relates to a test pattern for measuring a contact resistance and method of manufacturing the same. In order to confirm that a contact resistance suitable for a semiconductor device before an actual process for manufacturing the device is performed, the present invention designs a test pattern for measuring the contact resistance depending on a design rule of a line contact actually applied to an actual device.Type: ApplicationFiled: December 28, 2001Publication date: May 29, 2003Applicant: Hynix Semiconductor Inc.Inventors: Ki Seog Kim, Young Seon You, Keun Woo Lee, Sung Kee Park
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Patent number: 6556493Abstract: A method for testing a memory cell of the semiconductor device includes the steps of determining a reference memory cell and setting a first trip point by measuring a first drain current of a reference memory cell, testing an erasure verifying memory cell to be tested at a room temperature, detecting a fourth drain current by measuring the erasure verifying memory cell at a hot temperature and comparing the fourth drain current with the first drain current, varying the first drain trip point according to a current difference between the firs and the fourth drain currents and setting a second trip point of the erasure verifying memory cell according to the varied first trip point.Type: GrantFiled: December 28, 2001Date of Patent: April 29, 2003Assignee: Hynix Semiconductor Inc.Inventors: Young-Seon You, Yoon-Soo Jang, Mun-Hwa Lee, Tae-Kyu Kim
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Publication number: 20020136071Abstract: A method for testing a memory cell of the semiconductor device includes the steps of determining a reference memory cell and setting a first trip point by measuring a first drain current of a reference memory cell, testing an erasure verifying memory cell to be tested at a room temperature, detecting a fourth drain current by measuring the erasure verifying memory cell at a hot temperature and comparing the fourth drain current with the first drain current, varying the first drain trip point according to a current difference between the firs and the fourth drain currents and setting a second trip point of the erasure verifying memory cell according to the varied first trip point.Type: ApplicationFiled: December 28, 2001Publication date: September 26, 2002Inventors: Young-Seon You, Yoon-Soo Jang, Mun-Hwa Lee, Tae-Kyu Kim