Patents by Inventor Young Seong Lee
Young Seong Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160248047Abstract: A laminate for a light emitting device, includes a glass substrate, a random network of reliefs formed on the glass substrate, and a flattening layer formed on the network, wherein the network of reliefs are formed from a glass frit. The laminate for a light emitting device further includes a network inducing the scattering of light for efficiently extracting outward a loss of light at an interface between a glass substrate and an internal light extraction layer. The laminate is suitable for the industrial field of optical devices, such as organic light emitting diodes (OLEDs), backlights, lighting, and the like.Type: ApplicationFiled: October 7, 2014Publication date: August 25, 2016Inventors: Young-Seong LEE, Jin-Woo HAN
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Patent number: 9412958Abstract: A transparent diffusive OLED substrate includes the following successive elements or layers: (a) a transparent flat substrate made of mineral glass having a refractive index n1 of between 1.48 and 1.58, (b) a monolayer of mineral particles attached to one side of the substrate by means of a low index mineral binder having a refractive index n2 of between 1.45 and 1.61, and (c) a high index layer made of an enamel having a refractive index n4 between 1.82 and 2.10 covering the monolayer of mineral particles, the mineral particles having a refractive index n3 between n2+0.08 and n4?0.08 and protruding from the low index mineral binder so as to be directly in contact with the high index layer, thereby forming a first diffusive interface between the mineral particles and the low index binder, and a second diffusive interface between the mineral particles and the high index layer.Type: GrantFiled: June 13, 2014Date of Patent: August 9, 2016Assignee: SAINT-GOBAIN GLASS FRANCEInventors: Guillaume Lecamp, Vincent Sauvinet, Young Seong Lee
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Patent number: 9391300Abstract: A method of producing a transparent diffusive OLED substrate includes lapping one face or both faces of a flat translucent glass substrate with an abrasive slurry, so as to obtain a flat glass substrate with at least one roughened surface having a roughness profile with an arithmetical mean deviation Ra of between 0.1 ?m and 2.0 ?m; coating the roughened surface or one of the roughened surfaces with a high index glass frit having a refractive index of at least 1.7, the amount of the high index glass frit being sufficient to completely cover the roughness profile of the roughened surface after melting of the frit, and heating the coated substrate to a temperature above the melting temperature of the high index glass frit and below the softening temperature of the underlying substrate, so as to form high index enamel on one of the roughened surfaces.Type: GrantFiled: September 24, 2013Date of Patent: July 12, 2016Assignee: SAINT-GOBAIN GLASS FRANCEInventors: Yechun Zhou, Young Seong Lee, Jean Philippe Schweitzer, Vincent Sauvinet
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Publication number: 20160155990Abstract: Provided is a laminate for a light emitting device. The laminate for a light emitting device includes a glass substrate having potassium or a glass substrate coated with a mineral layer containing potassium, and an internal light extraction layer formed from a glass frit on the glass substrate. The internal light extraction layer includes an interface void layer at an interface with the glass substrate or the mineral layer. The laminate has an interface void layer inducing the scattering of light for effectively extracting light, which is lost at the interface between the substrate and the internal light extraction layer, to the outside. The laminate is suitable for the fields of optical devices such as organic light emitting diodes (OLEDs), backlights, lighting industry, etc.Type: ApplicationFiled: July 16, 2014Publication date: June 2, 2016Inventors: Jin-Woo HAN, Young-Seong LEE
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Publication number: 20160126481Abstract: A transparent diffusive OLED substrate includes the following successive elements or layers: (a) a transparent flat substrate made of mineral glass having a refractive index n1 of between 1.48 and 1.58, (b) a monolayer of mineral particles attached to one side of the substrate by means of a low index mineral binder having a refractive index n2 of between 1.45 and 1.61, and (c) a high index layer made of an enamel having a refractive index n4 between 1.82 and 2.10 covering the monolayer of mineral particles, the mineral particles having a refractive index n3 between n2+0.08 and n4?0.08 and protruding from the low index mineral binder so as to be directly in contact with the high index layer, thereby forming a first diffusive interface between the mineral particles and the low index binder, and a second diffusive interface between the mineral particles and the high index layer.Type: ApplicationFiled: June 13, 2014Publication date: May 5, 2016Inventors: Guillaume LECAMP, Vincent SAUVINET, Young Seong LEE
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Publication number: 20160087228Abstract: A transparent diffusive OLED substrate includes the following successive elements or layers: a transparent flat substrate made of mineral glass having a refractive index of between 1.45 and 1.65, a rough low index layer including mineral particles, the mineral particles being bonded to one side of the substrate by means of a low index enamel, the mineral particles near, at or protruding from the enamel's surface creating a surface roughness characterized by an arithmetical mean deviation Ra comprised between 0.15 and 3 ?m, the mineral particles and enamel both having a refractive index of between 1.45 and 1.65; a high index planarization layer made of an enamel having a refractive index comprised between 1.8 and 2.1 covering the rough low index layer (b).Type: ApplicationFiled: April 29, 2014Publication date: March 24, 2016Inventors: Guillaume LECAMP, Vincent SAUVINET, Young Seong LEE
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Publication number: 20150255753Abstract: A method of producing a transparent diffusive OLED substrate includes lapping one face or both faces of a flat translucent glass substrate with an abrasive slurry, so as to obtain a flat glass substrate with at least one roughened surface having a roughness profile with an arithmetical mean deviation Ra of between 0.1 ?m and 2.0 ?m; coating the roughened surface or one of the roughened surfaces with a high index glass frit having a refractive index of at least 1.7, the amount of the high index glass frit being sufficient to completely cover the roughness profile of the roughened surface after melting of the frit, and heating the coated substrate to a temperature above the melting temperature of the high index glass frit and below the softening temperature of the underlying substrate, so as to form high index enamel on one of the roughened surfaces.Type: ApplicationFiled: September 24, 2013Publication date: September 10, 2015Inventors: Yechun Zhou, Young Seong Lee, Jean Philippe Schweitzer, Vincent Sauvinet
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Publication number: 20150179979Abstract: A layered structure for an organic light-emitting diode (OLED) device, the layered structure including a light-transmissive substrate and an internal extraction layer formed on one side of the light-transmissive substrate, in which the internal extraction layer includes (1) a scattering area containing scattering elements composed of solid particles and pores, the solid particles having a density that decreases as it goes away from the interface with the light-transmissive substrate, and the pores having a density that increases as it goes away from the interface with the light-transmissive substrate, and (2) a free area where no scattering elements are present, formed from the surface of the internal extraction layer, which is opposite to the interface, to a predetermined depth.Type: ApplicationFiled: June 14, 2013Publication date: June 25, 2015Inventors: Young Seong Lee, Jin Woo Han, Ji Woong Baek
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Publication number: 20150144900Abstract: A layered structure for an organic light-emitting diode (OLED) device, the layered structure including a light-transmissive substrate and an internal extraction layer formed on one side of the light-transmissive substrate, in which the internal extraction layer includes (1) a scattering area containing scattering elements composed of solid particles and pores, the solid particles having a density that decreases as it goes away from the interface with the light-transmissive substrate, and the pores having a density that increases as it goes away from the interface with the light-transmissive substrate, and (2) a free area where no scattering elements are present, formed from the surface of the internal extraction layer, which is opposite to the interface, to a predetermined depth.Type: ApplicationFiled: June 14, 2013Publication date: May 28, 2015Applicant: SAINT-GOBAIN GLASS FRANCEInventors: Young Seong Lee, Jin Woo Han, Ji Woong Baek
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Patent number: 7675128Abstract: Embodiments relate to a method for forming a gate insulating layer, which may include forming a device isolation layer being divided into a device active region and a device isolation region, growing a first oxide layer at an entire surface of the semiconductor substrate as a gate insulating layer, performing a first annealing process to form a diffusion barrier layer an interface between the first oxide layer and the device active region, etching and removing a first oxide layer and a diffusion barrier layer of the core power source wiring region by masking the input/output power source wiring region, growing a second oxide layer on the core power source wiring region, and performing a second annealing process to form an NO gate oxide layer on which an N-rich oxide layer at an interface of the core power source wiring region.Type: GrantFiled: January 12, 2009Date of Patent: March 9, 2010Assignee: Dongbu HiTek Co., Ltd.Inventor: Young Seong Lee
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Publication number: 20100041200Abstract: A semiconductor transistor device and a method for manufacturing the same are provided. The method includes forming a silicon epitaxial layer having a predetermined thickness in source and drain diffusion regions of a silicon semiconductor substrate and forming a source and drain junction by ion implantation and rapid annealing in the silicon semiconductor substrate in which the silicon epitaxial layer is formed. The semiconductor transistor device includes a silicon epitaxial layer formed to have a predetermined thickness in source and drain diffusion regions of a silicon semiconductor substrate. Thus, since a salicide layer is used without increase of leakage current, the transistor device having low power and high performance can be manufactured.Type: ApplicationFiled: August 11, 2009Publication date: February 18, 2010Inventor: Young Seong Lee
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Patent number: 7589027Abstract: Provided is a method of manufacturing a semiconductor device. A first gate oxide layer is formed on a semiconductor substrate in which a core region and an input/output region are defined. The first gate oxide layer of the core region is selectively removed, and a second gate oxide layer is formed under the first gate oxide layer of the input/output region and on the semiconductor substrate of the core region. Nitrogen annealing is performed to form a nitrogen-rich oxide layer under the second gate oxide layer. An additional thermal process is performed to diffuse nitrogen segregated on an interface between the first gate oxide layer and the second gate oxide layer of the input/output region to a surface of the semiconductor substrate. Impurities generated during the additional thermal process are discharged to the outside.Type: GrantFiled: December 26, 2006Date of Patent: September 15, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Young Seong Lee
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Publication number: 20090127671Abstract: Embodiments relate to a method for forming a gate insulating layer, which may include forming a device isolation layer being divided into a device active region and a device isolation region, growing a first oxide layer at an entire surface of the semiconductor substrate as a gate insulating layer, performing a first annealing process to form a diffusion barrier layer an interface between the first oxide layer and the device active region, etching and removing a first oxide layer and a diffusion barrier layer of the core power source wiring region by masking the input/output power source wiring region, growing a second oxide layer on the core power source wiring region, and performing a second annealing process to form an NO gate oxide layer on which an N-rich oxide layer at an interface of the core power source wiring region.Type: ApplicationFiled: January 12, 2009Publication date: May 21, 2009Inventor: Young Seong Lee
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Patent number: 7524720Abstract: A method of manufacturing a semiconductor device is provided. The method includes the steps of forming a gate oxide layer including an oxide layer containing a large amount of nitrogen on a semiconductor substrate on which an input/output (I/O) region including an NMOS region and a PMOS region are defined, forming a polysilicon on the gate oxide layer, selectively removing the polysilicon on the PMOS region, selectively removing the gate oxide layer on the PMOS region, forming a pure SiO2 layer on the semiconductor substrate of the PMOS region, removing a surface oxide layer on the remaining polysilicon generated when the pure SiO2 layer is formed, and forming a gate electrode polysilicon on the entire surface including the remaining polysilicon.Type: GrantFiled: December 26, 2006Date of Patent: April 28, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Young Seong Lee
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Patent number: 7494879Abstract: Embodiments relate to a method for forming a gate insulating layer, which may include forming a device isolation layer being divided into a device active region and a device isolation region, growing a first oxide layer at an entire surface of the semiconductor substrate as a gate insulating layer, performing a first annealing process to form a diffusion barrier layer an interface between the first oxide layer and the device active region, etching and removing a first oxide layer and a diffusion barrier layer of the core power source wiring region by masking the input/output power source wiring region, growing a second oxide layer on the core power source wiring region, and performing a second annealing process to form an NO gate oxide layer on which an N-rich oxide layer at an interface of the core power source wiring region.Type: GrantFiled: December 26, 2006Date of Patent: February 24, 2009Assignee: Dongbu HiTek Co., Ltd.Inventor: Young Seong Lee
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Publication number: 20070171741Abstract: Disclosed is a method of curing a failure of an analog device, wherein the operational range of a transistor is optimized, thereby curing a failure in the analog device and enhancing a yield. In the method, the target of the 1.5V high transistor is modified to a fast condition, thereby eliminating the ring type failure phenomenon caused by Fmax. To this end, the manufacturing margin of a threshold voltage is set as 100 mV, the control specification of GC CD (Critical dimension) is set as ±0.013 ?m, and the thickness specification of a gate oxide is set as 23±1 ?.Type: ApplicationFiled: December 28, 2006Publication date: July 26, 2007Inventors: Young Seong Lee, Kye Lee
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Publication number: 20070161175Abstract: Embodiments relate to a method for forming a gate insulating layer, which may include forming a device isolation layer being divided into a device active region and a device isolation region, growing a first oxide layer at an entire surface of the semiconductor substrate as a gate insulating layer, performing a first annealing process to form a diffusion barrier layer an interface between the first oxide layer and the device active region, etching and removing a first oxide layer and a diffusion barrier layer of the core power source wiring region by masking the input/output power source wiring region, growing a second oxide layer on the core power source wiring region, and performing a second annealing process to form an NO gate oxide layer on which an N-rich oxide layer at an interface of the core power source wiring region.Type: ApplicationFiled: December 26, 2006Publication date: July 12, 2007Inventor: Young Seong Lee
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Publication number: 20070161212Abstract: A method for manufacturing a semiconductor device having a fuse area and a pad area. An inter-layer dielectric layer is deposited over a semiconductor substrate having a metal interconnection. A protection layer is deposited over the inter-layer dielectric layer. A photoresist mask is used to define areas to be etched in the fuse area and a pad area. The protection layer and the inter-layer dielectric layer are etched in the pad area and the fuse area, thereby exposing the metal interconnection in the pad area, and removing the dielectric material to a predetermined depth in a fuse area, using an etching gas including a first component. The first etching process is stopped. A second etching process is performed for selectively etching a surface of the metal interconnection using an etching gas including a second component.Type: ApplicationFiled: December 26, 2006Publication date: July 12, 2007Inventor: Young Seong Lee
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Patent number: 6855616Abstract: A method of producing a semiconductor device, wherein after a trench is formed on a field region of a semiconductor substrate, an adsorption reaction of TEOS and a decomposition/recomposition reaction of TEOS using as a catalyst oxygen atoms decomposed from O3 are independently and repeatedly performed. As disclosed, the oxide layer can be buried in the trench with a fine width without generating voids therein, increasing electrical property of the semiconductor device.Type: GrantFiled: October 27, 2003Date of Patent: February 15, 2005Assignee: Dongbu Electronics Co., Ltd.Inventor: Young Seong Lee
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Publication number: 20040126930Abstract: A method of producing a semiconductor device, wherein after a trench is formed on a field region of a semiconductor substrate, an adsorption reaction of TEOS and a decomposition/recomposition reaction of TEOS using as a catalyst oxygen atoms decomposed from O3 are independently and repeatedly performed. As disclosed, the oxide layer can be buried in the trench with a fine width without generating voids therein, increasing electrical property of the semiconductor device.Type: ApplicationFiled: October 27, 2003Publication date: July 1, 2004Inventor: Young Seong Lee