Abstract: An organic light emitting device including: a substrate; a first electrode; a second electrode; and an organic layer interposed between the first electrode and the second electrode and including an emission layer, wherein one of the first electrode and the second electrode is a reflective electrode and the other is a semitransparent or transparent electrode, and wherein the organic layer includes a layer having at least one of the compounds having at least one carbazole group, and a flat panel display device including the organic light emitting device. The organic light emitting device has low driving voltage, excellent current density, high brightness, excellent color purity, high efficiency, and long lifetime.

Abstract: A memory device according to the present invention may comprise: a memory cell array in which memory cells of a latch structure are connected in matrix form to word lines and bit line pairs composed of bit lines and inverted bit lines; and a driving circuit which, during an ON period in which the word lines activate first memory cells connected to the corresponding word lines, continuously programs or reads n (n is a natural number of 2 or more) second memory cells among the first memory cells through n first bit line pairs.

Abstract: A low-noise amplifier in a receiver supporting a beam forming function may selectively change a phase shift for beam steering. The low-noise amplifier may include first and second transistors and a variable capacitance circuit connected to a gate of the second transistor. The variable capacitance circuit may selectively change capacitance thereof based on a capacitance control signal applied thereto according to beam-forming information, where the changed capacitance correspondingly causes a phase change in an output signal of the low-noise amplifier. A similar scheme may be employed for amplifiers in transmit signal paths to steer a transmit beam.

Abstract: According to various embodiments of the present invention, disclosed is an electronic device comprising: a first antenna element configured so as to transmit and receive a signal of a first frequency band or a second frequency band; a second antenna element configured so as to transmit and receive the signal of the first frequency band or the second frequency band; a first RF block electrically connected to the first antenna element and the second antenna element and including a first transmission and reception circuit and a second transmission and reception circuit; an RF reception circuit for receiving the signal of the first frequency band or the second frequency band from the first antenna element or the second antenna element; and a transceiver, wherein the first transmission and reception circuit processes the signal of the first frequency band or the second frequency band, the second transmission and reception circuit processes the signal of the first frequency band or the second frequency band, and th

Abstract: An electronic device includes a display device, which may be fabricated using a described method. The display device includes a glass substrate including a first surface, a second surface opposite the first surface, and a side surface between the first surface and the second surface, an outermost structure on the first surface of the glass substrate and located adjacent to an edge of one side of the glass substrate, and a display area including a plurality of light emitting areas on the first surface of the glass substrate and located farther from the edge of the one side of the glass substrate than the outermost structure is. A minimum distance from the side surface of the glass substrate to the outermost structure is equal to 130 ?m or less.

Abstract: Disclosed is a core for a current transformer, which forms an upper core in a round shape, and is disposed at a position lower than the center of a power line having both ends of the upper core received, thereby minimizing the stress of a magnetic path, and increases the permeability, thereby enhancing the magnetic induction efficiency. The disclosed core for the current transformer includes an upper core curved in a semi-circular shape to have a receiving groove formed therein, and having both ends extended downwards to be disposed to be spaced apart from each other and a lower core disposed on the lower portion of the upper core, and having both ends extended upwards to be disposed to face both ends of the upper core.

Abstract: A memory device according to the present invention comprises: a memory cell array in which memory cells are connected to wordlines and bitlines in a matrix form; and a control circuit for programming the memory cells or controlling a read operation, according to a start address, a burst length, a latency length, and a program or read command which are transmitted from a host, wherein the control circuit may comprise: a pulse generation unit for generating register pulses and counter pulses in synchronization with an operation clock; and a counter that sets the start address in synchronization with the register pulses, counts the number of counter pulses corresponding to the sum of the latency length and the burst length, and increases an address from the start address to the sum of the start address and the burst length.

Abstract: A thermoplastic resin composition includes base resin, which includes a polycarbonate resin and an acrylonitrile-butadiene-styrene (ABS) resin, and an additive. The ABS resin includes a rubber-modified vinyl-based graft copolymer resin, an aromatic vinyl-vinyl cyanide-based copolymer resin. The polycarbonate resin has a weight-average molecular weight of 20,000 g/mol to 40,000 g/mol, and the rubber-modified vinyl-based graft copolymer resin comprises 50 wt % to 60 wt % of polybutadiene rubber based on a total wt % of the thermoplastic resin composition.

Abstract: The memory device according to an embodiment may comprise a memory cell array in which memory cells of a latch structure are connected in a matrix form to word lines and bit lines and a peripheral circuit configured to supply a first voltage to the memory cells only in a developing section of a read operation for the memory cells and supply a second voltage which maintains data of the memory cells and lower than the first voltage in other sections. The peripheral circuit may be configured to supply the second voltage to the memory cells in all sections of a write operation for the memory cells.

Abstract: A memory device according to the present invention comprises: a memory cell array in which memory cells are connected to wordlines and bitlines in a matrix form; and a control circuit for programming the memory cells or controlling a read operation, according to a start address, a burst length, a latency length, and a program or read command which are transmitted from a host, wherein the control circuit may comprise: a pulse generation unit for generating register pulses and counter pulses in synchronization with an operation clock; and a counter that sets the start address in synchronization with the register pulses, counts the number of counter pulses corresponding to the sum of the latency length and the burst length, and increases an address from the start address to the sum of the start address and the burst length.

Abstract: A memory device according to the present invention may comprise: a memory cell array in which memory cells are connected in matrix form to word lines and bit lines; a plurality of mergers connected in series to transfer data that is read from a selected memory cell among the memory cells included in the memory cell array and is transformed into one of a direct current form or a pulse form; and a sorter that synchronizes an edge of first output data, output by one of the plurality of mergers, with an edge of a control pulse, thereby delaying the edge of the first output data. First data, which is either data bit “0” or data bit “1”, can be input to the mergers in the form of a direct current of first logic, and second data, which is another piece of data, can be input to the mergers in the form of a pulse that changes from the first logic to the second logic and back to the first logic.

Abstract: A memory device according to the present invention may comprise: a memory cell array in which memory cells of a latch structure are connected in matrix form to word lines and bit line pairs composed of bit lines and inverted bit lines; and a driving circuit which, during an ON period in which the word lines activate first memory cells connected to the corresponding word lines, continuously programs or reads n (n is a natural number of 2 or more) second memory cells among the first memory cells through n first bit line pairs.

Abstract: A thermoplastic resin composition includes base resin, which includes a polycarbonate resin and an acrylonitrile-butadiene-styrene (ABS) resin, and an additive. The ABS resin includes a rubber-modified vinyl-based graft copolymer resin, an aromatic vinyl-vinyl cyanide-based copolymer resin. The polycarbonate resin has a weight-average molecular weight of 20,000 g/mol to 40,000 g/mol, and the rubber-modified vinyl-based graft copolymer resin comprises 50 wt % to 60 wt % of polybutadiene rubber based on a total wt % of the thermoplastic resin composition.

Abstract: Disclosed herein is a latch circuit capable of preventing an output failure caused due to simultaneous transition of a control signal and an input signal. The latch circuit according to the present invention generates a separate control adjustment signal CTR using the control signal Control and the input signal In and uses the control adjustment signal CTR, instead of the control signal for a latch operation. Accordingly, when the control signal and the input signal transition at the same time, the control adjustment signal is processed not to transition during a transition interval of the input signal, thereby preventing a metastability problem that occurred in the existing latch circuit.

Abstract: A conductive layer may be fabricated on a semiconductor substrate by loading a silicon substrate in to a chamber whose inside temperature is at a loading temperature in the range of approximately 250° C. to approximately 300° C., increasing the inside temperature of the chamber from the loading temperature to a process temperature, and sequentially stacking a single crystalline silicon layer and a polycrystalline silicon layer over the silicon substrate by supplying a silicon source gas and an impurity source gas in to the chamber, where the chamber may be, for example, a CVD chamber or a LPCVD chamber.

Abstract: A conductive layer may be fabricated on a semiconductor substrate by loading a silicon substrate in to a chamber whose inside temperature is at a loading temperature in the range of approximately 250° C. to approximately 300° C., increasing the inside temperature of the chamber from the loading temperature to a process temperature, and sequentially stacking a single crystalline silicon layer and a polycrystalline silicon layer over the silicon substrate by supplying a silicon source gas and an impurity source gas in to the chamber, where the chamber may be, for example, a CVD chamber or a LPCVD chamber.

Abstract: A semiconductor memory device capable of synchronous/asynchronous operation and data input/output method thereof are provided. The semiconductor memory device includes a memory cell array, a peripheral circuit configured to write data to a cell in the memory cell array and to read data from the cell, and a bypass control unit configured to control a late write operation and a bypass operation of the peripheral circuit according to mode conversion of the semiconductor memory device. Accordingly, data coherency can be maintained. In addition, dummy cycle time that may occur during the mode conversion can be prevented by generating a mode conversion signal only in response to toggling of a clock signal.

Abstract: There is provided a bit line voltage supply circuit for reducing leakage current flowing from bit lines to a memory cell without substantially deteriorating the performance of a semiconductor memory device. A bit line voltage switch applies a first supply voltage to a bit line pair in response to a first switch control signal, and applies a second supply voltage having a lower voltage than the first supply voltage to the bit line pair in response to a second switch control signal. A bit line voltage controller controls the first and second switch control signals so that the second supply voltage is supplied to the bit line pair during a standby mode, and the first supply voltage is supplied to the bit line pair when the semiconductor memory device changes from the standby mode to an operational mode for a predetermined time period.

Abstract: A semiconductor memory device capable of synchronous/asynchronous operation and data input/output method thereof are provided. The semiconductor memory device includes a memory cell array, a peripheral circuit configured to write data to a cell in the memory cell array and to read data from the cell, and a bypass control unit configured to control a late write operation and a bypass operation of the peripheral circuit according to mode conversion of the semiconductor memory device. Accordingly, data coherency can be maintained. In addition, dummy cycle time that may occur during the mode conversion can be prevented by generating a mode conversion signal only in response to toggling of a clock signal.

Abstract: A method and apparatus for repairing defective cells for each section word line. The repairing apparatus includes an address comparison unit and a repairing unit. The address comparison unit compares a main address of a defective address, indicating the location of a defective cell, to a main address of an external address. The address comparison unit determines when a redundancy main word line corresponding to the main address of the external address is activated. The repairing unit activates a redundancy section word line corresponding to a section address of the external address from among a plurality of redundancy section word lines connected to the redundancy main word line in order to repair the defective cell. Accordingly, defective cells are repaired for each section word line while minimizing the area of the repairing apparatus. Randomly generated defective cells can be efficiently repaired.