Abstract: The present invention relates to a 2,7-substituted pyrrolo[2,1-f][1,2,4]triazine compound having a protein kinase inhibitory activity, a pharmaceutically acceptable salt thereof, and a pharmaceutical composition for the prevention, alleviation, or treatment of diseases induced by abnormal cell growth containing the compounds as active ingredients, and the novel cyclic 2,7-substituted pyrrolo[2,1-f][1,2,4]triazine compounds of the present invention exhibit excellent inhibitory effects on various protein kinases involved in growth factor signaling pathways. Therefore, they are useful as preventives, alleviators, or therapeutics for diseases characterized by abnormal cell growth induced by these protein kinases.

Abstract: An embodiment of the present disclosure relates to a polyolefin polymer including a core portion and a shell portion, wherein the core portion has a density of 0.857 g/cm3 to 0.910 g/cm3, the shell portion has a density of 0.890 g/cm3 to 0.940 g/cm3, and the density of the shell portion is higher than that of the core portion, and a polymerization system and polymerization method of producing the same.

Abstract: The present disclosure relates to an antenna RF module, an RF module assembly including the antenna RF modules, and an antenna apparatus including the RF module assembly. Particularly, the antenna RF module includes an RF module, a radiation element module arranged on a first side of the RF filter, and an amplification unit board arranged on a second side of the RF filter, an analog amplification element being mounted on the amplification unit board. A plurality of antenna RF modules constitute the RF module assembly, and the RF module assembly and an antenna housing constitute the antenna apparatus. Accordingly, a radome that interrupts dissipation of heat to in front of an antenna is unnecessary, and heat generated from heat generating elements of the antenna apparatus is spatially separated. Thus, it is possible that the heat is dissipated in a distributed manner toward the front and rear directions of the antenna apparatus. The effect of greatly improving performance in heat dissipation can be achieved.

Abstract: The present invention relates to a polyester nonwoven fabric with suppressed reduction in physical properties by a tufting process, a method for manufacturing same, and a backing fabric for a carpet, comprising same and, in particular, to: a polyester nonwoven fabric in which, by controlling the physical properties of fibers of a first component filament and a second filament, a reduction in physical properties is remarkably suppressed before/after a tufting process, thus enabling the manufacture of a carpet backing fabric with excellent mechanical properties; a method for manufacturing same; and a backing fabric for a carpet, manufactured thereby.

Abstract: The present disclosure relates to a method for manufacturing core-shell particles using carbon monoxide, and more particularly, to a method for manufacturing core-shell particles, the method of which a simple and fast one-pot reaction enables particle manufacturing to reduce process costs, facilitate scale-up, change various types of core and shell metals, and form a multi-layered shell by including the steps of adsorbing carbon monoxide on a transition metal for a core, and reacting carbon monoxide adsorbed on the surface of the transition metal for the core, a metal precursor for a shell, and a solvent to form particles with a core-shell structure having a reduced metal shell layer formed on a transition metal core.

Abstract: An apparatus for combining PCBs may include a pick-up mechanism, a gripping mechanism and a combining mechanism. The pick-up mechanism may pick-up the PCBs connected with each other by a flexible connection member. The gripping mechanism may grip a frame. The combining mechanism may press the flexible connection member using the frame to combine the PCBs with the frame. The process for combining the PCBs with the frame may be automatically performed so that a time for combining the PCBs with the frame is reduced and errors related to the combining process are decreased.

Abstract: An apparatus for combining PCBs may include a pick-up mechanism, a gripping mechanism and a combining mechanism. The pick-up mechanism may pick-up the PCBs connected with each other by a flexible connection member. The gripping mechanism may grip a frame. The combining mechanism may press the flexible connection member using the frame to combine the PCBs with the frame. The process for combining the PCBs with the frame may be automatically performed so that a time for combining the PCBs with the frame is reduced and errors related to the combining process are decreased.

Abstract: A method of aligning a wafer includes recognizing images of the wafer accommodated on a work table and a notch of the wafer using a camera, designating at least one notch point of the notch in a recognized image, producing at least one reference line using the designated notch point in the recognized image, designating a center point of the reference line in the recognized image, producing an imaginary line having an angle with respect to the reference line from the center point of the reference line in the recognized image, producing a center line of the wafer using the imaginary line in the recognized image, and aligning the wafer using an alignment apparatus to allow the center line of the wafer and an alignment line of the work table to be matched.

Abstract: Provided is a printed circuit board having a bump interconnection structure that improves reliability between interconnection layers. Also provided is a method of fabricating the printed circuit board and semiconductor package using the printed circuit board. According to one embodiment, the printed circuit board includes a plurality of bumps formed on a resin layer between a first interconnection layer and a second interconnection layer. The second interconnection layer includes insertion holes corresponding to upper portions of the bumps so that the upper portions of the bumps protrude from the second interconnection layer. The upper portion of at least one of the bumps includes a rivet portion having a diameter greater that the diameter of the corresponding insertion hole to reliably interconnect the first and second interconnection layers.

Abstract: A method of aligning a wafer includes recognizing images of the wafer accommodated on a work table and a notch of the wafer using a camera, designating at least one notch point of the notch in a recognized image, producing at least one reference line using the designated notch point in the recognized image, designating a center point of the reference line in the recognized image, producing an imaginary line having an angle with respect to the reference line from the center point of the reference line in the recognized image, producing a center line of the wafer using the imaginary line in the recognized image, and aligning the wafer using an alignment apparatus to allow the center line of the wafer and an alignment line of the work table to be matched.

Abstract: A method of inspecting the alignment of a second structure with respect to a first structure, including emitting light from a first plane of a first structure to a second plane of a second structure in a first direction perpendicular to the first plane of the first structure, the first plane and the second plane facing each other. The incident light can be reflected from the second plane toward the first plane in a second direction parallel with the first direction. The position of the reflected light can be detected to inspect the alignment of the second structure with respect to the first structure.

Abstract: According to an example embodiment, a method of fabricating an electronic device may include preparing a substrate with a first area and a second area. A metal interconnection may be formed on the substrate extending from the first area to the second area. An insulating layer may be formed on the substrate. A sacrificial pattern electrically connected to the metal interconnection and serving as a sacrificial anode for cathodic protection against corrosion of the metal interconnection may be formed on the second area. An opening to expose the metal interconnection on the first area may be formed by patterning the insulating layer. An electronic device fabricated by a method according to an example embodiment may include a substrate, a metal interconnection, an insulating layer, and/or a sacrificial pattern.

Abstract: Provided is a printed circuit board having a bump interconnection structure that improves reliability between interconnection layers. Also provided is a method of fabricating the printed circuit board and semiconductor package using the printed circuit board. According to one embodiment, the printed circuit board includes a plurality of bumps formed on a resin layer between a first interconnection layer and a second interconnection layer. The second interconnection layer includes insertion holes corresponding to upper portions of the bumps so that the upper portions of the bumps protrude from the second interconnection layer. The upper portion of at least one of the bumps includes a rivet portion having a diameter greater that the diameter of the corresponding insertion hole to reliably interconnect the first and second interconnection layers.

Abstract: A stack type semiconductor package, and a method of fabricating the same are provided. The stack type semiconductor package may include a lower unit package and an upper unit package. The lower unit package may include a substrate, and a semiconductor chip on an upper surface of the substrate. A bump may be on an upper surface of the substrate, and a protecting layer, covering the semiconductor chip, may be formed. The protecting layer may include a via hole partially exposing the bump. The upper unit package may be on the protecting layer, and may include an internal connection solder ball on a lower surface of the upper unit package. The internal connection solder ball may be inserted into the via hole and connected to the bump.