Abstract: Provided is an optical system which may acquire a hyperspectral image by acquiring a spectral image of an object to be measured, which includes, to collect spectral data and train the neural network, an image forming part forming an image from an object to be measured and transmitting collimated light, a slit moving to scan the incident image and passing and outputting a part of the formed image, and a first optical part obtaining spectral data by splitting light of the image received through the slit by wavelength. Also, the system includes, to decompose overlapped spectral data and to infer hyperspectral image data through the trained neural network, an image forming part forming an image from an object to be measured and transmitting collimated light, and a first optical part obtaining spectral data by splitting light of the received image by wavelength.

Abstract: A flexible display device includes a flexible substrate that includes a first side; a display unit disposed in a first region of the first side and that includes a plurality of pixels; and a pad portion disposed in a second region of the first side and that includes a plurality of pad electrodes. The flexible substrate includes a stepwise recess portion disposed along an edge of the first side on which end portions of the pad electrodes are provided.

Abstract: A semiconductor integrated circuit device may include a target PMOS transistor, a target NMOS transistor, a first stress-applying circuit, a second stress-applying circuit, a third stress-applying circuit and a fourth stress-applying circuit. An inverter may include the target PMOS transistor and the NMOS transistor. The first stress-applying circuit may be configured to apply a first DC level to a gate of the target PMOS transistor. The second stress-applying circuit may be configured to apply a second DC level to a gate of the target NMOS transistor. The third stress-applying circuit may be configured to apply an AC voltage shape to the gate of the target NMOS transistor. The fourth stress-applying circuit may be configured to apply the AC voltage to a drain of the target NMOS transistor.

Abstract: A flexible display device includes a flexible substrate that includes a first side; a display unit disposed in a first region of the first side and that includes a plurality of pixels; and a pad portion disposed in a second region of the first side and that includes a plurality of pad electrodes. The flexible substrate includes a stepwise recess portion disposed along an edge of the first side on which end portions of the pad electrodes are provided.

Abstract: A semiconductor device includes a first pre-stress block suitable for generating a first load signal, which corresponds to an active signal during an active mode and/or to a high voltage level during a precharge mode, in response to a stress section signal; a first delay amount reflection block suitable for reflecting a first delay amount in the first load signal in response to one or more first delay amount control signals; and a first main stress block suitable for generating a word line driving control signal, which corresponds to the active signal during the active mode and the high voltage level during the precharge mode, in response to the stress section signal and the first load signal.

Abstract: A semiconductor device includes a first pre-stress block suitable for generating a first load signal, which corresponds to an active signal during an active mode and/or to a high voltage level during a precharge mode, in response to a stress section signal; a first delay amount reflection block suitable for reflecting a first delay amount in the first load signal in response to one or more first delay amount control signals; and a first main stress block suitable for generating a word line driving control signal, which corresponds to the active signal during the active mode and the high voltage level during the precharge mode, in response to the stress section signal and the first load signal.

Abstract: A semiconductor integrated circuit device may include a target PMOS transistor, a target NMOS transistor, a first stress-applying circuit, a second stress-applying circuit, a third stress-applying circuit and a fourth stress-applying circuit. An inverter may include the target PMOS transistor and the NMOS transistor. The first stress-applying circuit may be configured to apply a first DC level to a gate of the target PMOS transistor. The second stress-applying circuit may be configured to apply a second DC level to a gate of the target NMOS transistor. The third stress-applying circuit may be configured to apply an AC voltage shape to the gate of the target NMOS transistor. The fourth stress-applying circuit may be configured to apply the AC voltage to a drain of the target NMOS transistor.

Abstract: An address detection circuit may include one or more address storage units, an initialization unit suitable for deleting an address stored in an address storage unit having a value greater than N, wherein the value is obtained by dividing a respective total input number that addresses have been inputted after the corresponding address is stored by a respective input number corresponding to the stored address, a detection unit suitable for detecting an address having an input number that is a reference number or more from the addresses stored in the one or more address storage units, and a selection unit suitable for selecting an address storage unit in which an address is not stored and storing an input address in the selected address storage unit.

Abstract: An address detection circuit may include one or more address storage units, an initialization unit suitable for deleting an address stored in an address storage unit having a value greater than N, wherein the value is obtained by dividing a respective total input number that addresses have been inputted after the corresponding address is stored by a respective input number corresponding to the stored address, a detection unit suitable for detecting an address having an input number that is a reference number or more from the addresses stored in the one or more address storage units, and a selection unit suitable for selecting an address storage unit in which an address is not stored and storing an input address in the selected address storage unit.