Abstract: Methods of forming integrated circuit capacitors include the steps of forming an electrically insulating layer on a face of a semiconductor substrate and then patterning the electrically insulating layer to define a contact hole therein. A barrier metal layer is then formed in at least a portion of the contact hole. A lower electrode metal layer is then formed on the barrier metal layer and then planarized by reflowing the lower electrode metal layer at a temperature greater than about 650.degree. C. in a nitrogen gas ambient, to define a lower capacitor electrode. A layer of material having a high dielectric constant is then formed on the lower capacitor electrode. An upper capacitor electrode is then formed on the dielectric layer, opposite the lower capacitor electrode. The dielectric layer may comprise Ba(Sr, Ti)O.sub.3, Pb(Zr, Ti)O.sub.3, Ta.sub.2 O.sub.5, SiO.sub.2, SiN.sub.3, SrTiO.sub.3, PZT, SrBi.sub.2 Ta.sub.2 O.sub.9, (Pb, La)(Zr, Ti)O.sub.3 and Bi.sub.4 Ti.sub.3 O.sub.12.

Abstract: A method of projection exposure utilizing a mask including a step of exposing an object by utilizing a transparent mask substrate of which the upper surface is slanted at a predetermined angle from a direction perpendicular to the light path and an opaque film pattern is formed at regular intervals on a lower surface of the mask substrate so that the phase difference between adjacent mask patterns occurs due to the slanted mask substrate, thereby reducing the minimum pitch available for pattern formation without a shorter-wavelength light source and without increasing NA by reducing the frequency difference .delta.v to the pitch d of the mask in a given wavelength of a light source and NA.