Abstract: Disclosed is fucosyllactose having antiviral activity and inhibitory activity against viral infection, and a method for preventing or treating a viral infection by administering a composition including fucosyllactose as an active ingredient to a subject in need thereof. It was found that 2?-fucosyllactose and 3-fucosyllactose, which are human milk oligosaccharides (HMOs), have antiviral activity, and in particular, 3-fucosyllactose in vitro and in vivo exhibits much higher antiviral activity and inhibitory activity against viral infection compared to 2?-fucosyllactose and is thus useful as an antiviral agent.

Abstract: Provided is a method for manufacturing a composition for increasing cognitive function.

Abstract: Provided is a compound of Chemical Formula 1: wherein: A1 represents Chemical Formula 1-a: the dotted line fuses with an adjacent ring, X is O or S, Ar1 is a substituted or unsubstituted C6-60 aryl or C2-60 heteroaryl containing at least one of N, O and S; D is deuterium; L is a single bond, or a substituted or unsubstituted C6-60 arylene or C2-60 heteroarylene containing at least one of N, O and S; A2 is Chemical Formula 1-b or 1-c: L1 and L2 are independently a single bond, or a substituted or unsubstituted C6-60 arylene or C2-60 heteroarylene containing at least one of N, O and S; Ar2 to Ar5 are independently a substituted or unsubstituted C6-60 aryl or C2-60 heteroaryl containing at least one of N, O and S; and n is 0 to 5, and an organic light-emitting device including the same.

Abstract: Ophthalmic therapeutic agents having as pharmaceutically active ingredient a poorly water soluble drug of formula 1 are described. Specifically, an ophthalmic formulation containing an inclusion complex of a poorly soluble drug of formula 1 enclosed in cyclodextrin or a cyclodextrin derivative in an aqueous solution of pH 10 or higher is administered to a patient in need of optic nerve protection.

Abstract: A pixel includes: a light emitting element; a first transistor including a gate electrode electrically connected to a first node, a second node to which a first power voltage for driving the light emitting element is to be applied, and a third node electrically connected to the light emitting element; and a bias control transistor configured to be controlled in operating timing thereof by a bias control signal, and configured to switch electrical connection between the second node and a bias power line for transmitting a bias voltage. In one frame period, a voltage level of the bias voltage to be applied to the second node sequentially increases.

Abstract: A system and method for operating a Unified Power Flow Controller (UPFC) connected to a SCADA (Supervisory Control and Data Acquisition) are disclosed. The UPFC automatic operation system receives power system data from the SCADA system, automatically determines UPFC's optimum operation conditions according to power system states. The system includes: a UPFC acting as a serial/parallel FACTS to control variables of a power system; a SCADA for periodically acquiring line data of the power system and state data of the UPFC; and an upper controller for analyzing data received from the SCADA, and determining an UPFC's optimum operation mode for each power system condition and UPFC's optimum set-point control commands.

Abstract: A system and method for operating a Unified Power Flow Controller (UPFC) connected to a SCADA (Supervisory Control and Data Acquisition) are disclosed. The UPFC automatic operation system receives power system data from the SCADA system, automatically determines UPFC's optimum operation conditions according to power system states. The system includes: a UPFC acting as a serial/parallel FACTS to control variables of a power system; a SCADA for periodically acquiring line data of the power system and state data of the UPFC; and an upper controller for analyzing data received from the SCADA, and determining an UPFC's optimum operation mode for each power system condition and UPFC's optimum set-point control commands.

Abstract: A method of cleaning a deposition chamber includes applying an RF power to a first region of a deposition chamber where a metal oxide layer is attached. The metal oxide layer in the first region is thicker than the metal oxide layer existing at a second region of the deposition chamber. The RF power increases a plasma sheath potential in the first region to a value that is greater than that of a plasma sheath potential in the second region. An etching gas is introduced into the deposition chamber to remove the metal oxide layer. The metal oxide layer attached to the deposition chamber may be rapidly removed by the in-situ process without opening of the deposition chamber.

Abstract: A semiconductor device having a metal layer pattern which prevents cracks from forming in insulating spaces. The semiconductor device includes a plurality of metal layers stacked vertically and a plurality of insulating layers, interposed vertically between the plurality of metal layers. A metal wiring pattern is formed on each of the plurality of metal layers. The wiring patterns are separated by insulating spaces, and the insulating spaces in each of the plurality of metal layers are vertically shifted with regard to the neighboring one of the plurality of metal layers.

Abstract: A semiconductor device having a metal layer pattern which prevents cracks from forming in insulating spaces. The semiconductor device includes a plurality of metal layers stacked vertically and a plurality of insulating layers, interposed vertically between the plurality of metal layers. A metal wiring pattern is formed on each of the plurality of metal layers. The wiring patterns are separated by insulating spaces, and the insulating spaces in each of the plurality of metal layers are vertically shifted with regard to the neighboring one of the plurality of metal layers.

Abstract: A method for forming a metal layer including the steps of heat treating a semiconductor substrate for a predetermined time at an intermediate temperature between 200.degree. C. and 400.degree. C., then depositing the metal layer on the semiconductor substrate at a temperature below 200.degree. C., in a vacuum, then thermally treating the metal layer at a temperature between 0.6 Tm-1.0 Tm (where Tm is the melting point of the metal layer), without breaking the vacuum, thereby reflowing the grains of the metal layer, and then gradually cooling the metal layer. Alternatively, the intermediate heat-treatment step can be performed after the metal layer is thermally treated, in which case, the metal layer should thereafter be rapidly cooled.