Abstract: The present invention relates to a polymerization reactor. The polymerization reactor according to one aspect of the present invention comprises: a housing including a supply part for supplying a reactant; a tube which is provided inside the housing and extends along the height direction of the housing; a first impeller including a blade which spirally surrounds the tube along the height direction of the housing; a second impeller which is provided inside the housing in order to enable the reactant to flow into the tube; and a partition wall which is provided to surround the second impeller along the circumferential direction.

Abstract: The present invention relates to a stirrer having grooves formed on the inside of a container in order to improve the degree of mixing, and the stirrer which is provided comprises: a plurality of projections formed on the inner surface of a stirrer container; and a plurality of grooves formed between the plurality of projections.

Abstract: A mixer and a reactor including the same are provided. According to one aspect of the present invention, the mixer includes a first piping part into which a first fluid flows, an elbow piping part having an inlet connected to the first piping part and an outlet provided at a location rotated by a predetermined angle from the inlet in a flow direction of the first fluid to have a curved flow path, and a second piping part connected to the elbow piping part to have a central axis perpendicular to a central axis of the first piping part so that a second fluid flows in a tangential direction of the elbow piping part when the second fluid flows into the elbow piping part.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a plurality of dummy gate lines parallel to each other in a first direction and extending in a second direction that is orthogonal to the first direction; a plurality of first dummy filling patterns between the plurality of dummy gate lines, the first dummy filling patterns parallel to each other in the first direction, and arranged apart from each other in the second direction; a plurality of first dummy vias on the plurality of first dummy filling patterns; and a plurality of first dummy wiring lines connected to the plurality of first dummy vias, the first dummy vias extending in the second direction, and parallel to each other in the first direction.

Abstract: The present invention relates to a stirrer having grooves formed on the inside of a container in order to improve the degree of mixing, and the stirrer which is provided comprises: a plurality of projections formed on the inner surface of a stirrer container; and a plurality of grooves formed between the plurality of projections.

Abstract: The present application relates to a mixer and a mixing method and, more specifically, to a pipe-type mixer for low-flow dispersion of immiscible liquids. The mixer, according to the present application, comprises: a pump(30) provided in a liquid transport section so as to supplement a deficient flow velocity, when materials to be mixed such as liquids are mixed through a continuous mixing step; and static mixers(22) suitable for the dispersion of the materials to be mixed by increasing a diameter of mixing parts(20) provided in a circulation pipe(10). Thus, a mixing rate of mixed materials can be more efficiently increased when the materials are mixed by using the static mixers(22).

Abstract: A semiconductor device includes a substrate; a device area of the substrate, the device area including a plurality of device unit cells; and a dummy cell array arranged around the device area. The dummy cell array includes a plurality of dummy unit cells repeatedly arranged in a first direction and a second direction perpendicular to the first direction, each of the dummy cell unit having a structure corresponding to a device unit cell. The device unit cell includes at least a first transistor in the device area. The structure of the dummy unit cell includes an active area and a gate line. For each dummy unit cell, the active area and the gate line extend beyond a cell boundary that defines the dummy unit cell.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a plurality of dummy gate lines parallel to each other in a first direction and extending in a second direction that is orthogonal to the first direction; a plurality of first dummy filling patterns between the plurality of dummy gate lines, the first dummy filling patterns parallel to each other in the first direction, and arranged apart from each other in the second direction; a plurality of first dummy vias on the plurality of first dummy filling patterns; and a plurality of first dummy wiring lines connected to the plurality of first dummy vias, the first dummy vias extending in the second direction, and parallel to each other in the first direction.

Abstract: A semiconductor device includes a substrate; a device area of the substrate, the device area including a plurality of device unit cells; and a dummy cell array arranged around the device area. The dummy cell array includes a plurality of dummy unit cells repeatedly arranged in a first direction and a second direction perpendicular to the first direction, each of the dummy cell unit having a structure corresponding to a device unit cell. The device unit cell includes at least a first transistor in the device area. The structure of the dummy unit cell includes an active area and a gate line. For each dummy unit cell, the active area and the gate line extend beyond a cell boundary that defines the dummy unit cell.

Abstract: Methods of manufacturing NOR-type flash memory device include forming a tunnel oxide layer on a substrate, forming a first conductive layer on the tunnel oxide layer, forming first mask patterns parallel to one another on the first conductive layer in a y direction of the substrate, and selectively removing the first conductive layer and the tunnel oxide layer using the first mask patterns as an etch mask. Thus, first conductive patterns and tunnel oxide patterns are formed, and first trenches are formed to expose the surface of the substrate between the first conductive patterns and the tunnel oxide patterns. A photoresist pattern is formed to open at least one of the first trenches, and impurity ions are implanted using the photoresist pattern as a first ion implantation mask to form an impurity region extending in a y direction of the substrate. The photoresist pattern is removed.

Abstract: Methods of manufacturing NOR-type flash memory device include forming a tunnel oxide layer on a substrate, forming a first conductive layer on the tunnel oxide layer, forming first mask patterns parallel to one another on the first conductive layer in a y direction of the substrate, and selectively removing the first conductive layer and the tunnel oxide layer using the first mask patterns as an etch mask. Thus, first conductive patterns and tunnel oxide patterns are formed, and first trenches are formed to expose the surface of the substrate between the first conductive patterns and the tunnel oxide patterns. A photoresist pattern is formed to open at least one of the first trenches, and impurity ions are implanted using the photoresist pattern as a first ion implantation mask to form an impurity region extending in a y direction of the substrate. The photoresist pattern is removed.

Abstract: A mobile terminal that displays menu information along a trace may include a memory unit to store menu information; a touch screen including a touch panel, the touch screen to display the menu information; and a controller to control the touch screen to display at least a portion of the menu information on a trace according to a dragged input signal corresponding to the trace. A method for displaying menu information on a display includes storing menu information including a menu item and sub-menu items corresponding to the menu item, receiving a dragged input signal on the display, the dragged input signal beginning at a start point, and displaying the sub-menu items on a trace corresponding to the dragged input signal, the menu item arranged at the start point.

Abstract: Provided is a method for fabricating a semiconductor device having reduced contact resistance. In the method, gate patterns defining a narrow opening and a wide opening are formed having an upper portion of a predetermined region of a semiconductor substrate. After gate spacers are formed on sidewalls of the gate patterns, an ion implantation process that uses the gate patterns and the gate spacers as an ion mask is performed to form a plug doped region in a portion of the semiconductor substrate that is located below the wide opening. At this point, the gate spacers are formed to expose a portion of a bottom surface of the wide opening and to fill a lower portion of the narrow opening.

Abstract: Provided is a method for fabricating a semiconductor device having reduced contact resistance. In the method, gate patterns defining a narrow opening and a wide opening are formed having an upper portion of a predetermined region of a semiconductor substrate. After gate spacers are formed on sidewalls of the gate patterns, an ion implantation process that uses the gate patterns and the gate spacers as an ion mask is performed to form a plug doped region in a portion of the semiconductor substrate that is located below the wide opening. At this point, the gate spacers are formed to expose a portion of a bottom surface of the wide opening and to fill a lower portion of the narrow opening.