Patents by Inventor Young Su Chung
Young Su Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240047521Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.Type: ApplicationFiled: October 17, 2023Publication date: February 8, 2024Inventors: Min-Chul SUN, Dae Won HA, Dong Hoon HWANG, Jong Hwa BAEK, Jong Min JEON, Seung Mo HA, Kwang Yong YANG, Jae Young PARK, Young Su CHUNG
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Patent number: 11830911Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.Type: GrantFiled: February 1, 2023Date of Patent: November 28, 2023Inventors: Min-Chul Sun, Dae Won Ha, Dong Hoon Hwang, Jong Hwa Baek, Jong Min Jeon, Seung Mo Ha, Kwang Yong Yang, Jae Young Park, Young Su Chung
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Publication number: 20230178595Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.Type: ApplicationFiled: February 1, 2023Publication date: June 8, 2023Inventors: Min-Chul Sun, Dae Won Ha, Dong Hoon Hwang, Jong Hwa Baek, Jong Min Jeon, Seung Mo Ha, Kwang Yong Yang, Jae Young Park, Young Su Chung
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Patent number: 11575002Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.Type: GrantFiled: March 25, 2021Date of Patent: February 7, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Chul Sun, Dae Won Ha, Dong Hoon Hwang, Jong Hwa Baek, Jong Min Jeon, Seung Mo Ha, Kwang Yong Yang, Jae Young Park, Young Su Chung
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Publication number: 20210233995Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.Type: ApplicationFiled: March 25, 2021Publication date: July 29, 2021Inventors: Min-Chul SUN, Dae Won HA, Dong Hoon HWANG, Jong Hwa BAEK, Jong Min JEON, Seung Mo HA, Kwang Yong YANG, Jae Young PARK, Young Su CHUNG
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Patent number: 10964782Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.Type: GrantFiled: December 16, 2019Date of Patent: March 30, 2021Inventors: Min-Chul Sun, Dae Won Ha, Dong Hoon Hwang, Jong Hwa Baek, Jong Min Jeon, Seung Mo Ha, Kwang Yong Yang, Jae Young Park, Young Su Chung
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Publication number: 20200119143Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: Min-Chul SUN, Dae Won HA, Dong Hoon HWANG, Jong Hwa BAEK, Jong Min JEON, Seung Mo HA, Kwang Yong YANG, Jae Young PARK, Young Su CHUNG
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Patent number: 10529801Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.Type: GrantFiled: March 23, 2018Date of Patent: January 7, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Chul Sun, Dae Won Ha, Dong Hoon Hwang, Jong Hwa Baek, Jong Min Jeon, Seung Mo Ha, Kwang Yong Yang, Jae Young Park, Young Su Chung
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Publication number: 20190096993Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.Type: ApplicationFiled: March 23, 2018Publication date: March 28, 2019Inventors: Min-Chul Sun, Dae Won Ha, Dong Hoon Hwang, Jong Hwa Baek, Jong Min Jeon, Seung Mo Ha, Kwang Yong Yang, Jae Young Park, Young Su Chung
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Patent number: 9299811Abstract: Semiconductor devices may include first and second fins that protrude from a substrate, extend in a first direction, and are separated from each other in the first direction. Semiconductor devices may also include a field insulating layer that is disposed between the first and second fins to extend in a second direction intersecting the first direction, an etch-stop layer pattern that is formed on the field insulating layer and a dummy gate structure that is formed on the etch-stop layer pattern.Type: GrantFiled: October 21, 2014Date of Patent: March 29, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Wook-Je Kim, Jae-Yup Chung, Jong-Seo Hong, Cheol Kim, Hee-Soo Kang, Hyun-Jo Kim, Hee-Don Jeong, Soo-Hun Hong, Sang-Bom Kang, Myeong-Cheol Kim, Young-Su Chung
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Publication number: 20160086943Abstract: A semiconductor device includes a substrate, an isolation layer on the substrate, and at least one active fin on the substrate. The isolation layer includes a first surface opposite a second surface. The first surface is contiguous with the substrate. The at least one active fin protrudes from the substrate and includes a first region having a side wall above the second surface of the isolation layer and a second region on the first region. The second region has an upper surface. The first region has a first width contiguous with the second surface of the isolation layer and a second width contiguous with the second region. The second width is 60% or greater than the first width (e.g., 60% to 100%).Type: ApplicationFiled: September 17, 2015Publication date: March 24, 2016Inventors: Sun Young LEE, Jae Young Park, Han Ki Lee, Bon Young Koo, Hong Bum Park, Young Su Chung, Jae Jong Han
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Publication number: 20150147860Abstract: Semiconductor devices may include first and second fins that protrude from a substrate, extend in a first direction, and are separated from each other in the first direction. Semiconductor devices may also include a field insulating layer that is disposed between the first and second fins to extend in a second direction intersecting the first direction, an etch-stop layer pattern that is formed on the field insulating layer and a dummy gate structure that is formed on the etch-stop layer pattern.Type: ApplicationFiled: October 21, 2014Publication date: May 28, 2015Inventors: Wook-Je Kim, Jae-Yup Chung, Jong-Seo Hong, Cheol Kim, Hee-Soo Kang, Hyun-Jo Kim, Hee-Don Jeong, Soo-Hun Hong, Sang-Bom Kang, Myeong-Cheol Kim, Young-Su Chung
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Patent number: 8148014Abstract: A composite anode active material including a transition metal; an intermetallic compound which includes the transition metal as one component and is capable of alloy formation with lithium; and carbon, where both the transition metal and the intermetallic compound have crystallinity, and the transition metal exists in a phase structurally separated from the intermetallic compound capable of alloy formation with lithium, where a content of the transition metal elements as both a metal and a component of the intermetallic compound may be less than 45 wt % based on the total weight of the transition metal and the intermetallic compound capable of alloy formation with lithium. The composite anode active material is a composite anode active material having a new structure, and includes a crystalline intermetallic compound, a crystalline transition metal, and carbon. In addition, an anode and lithium battery prepared using the composite anode active material have excellent charge-discharge characteristics.Type: GrantFiled: January 30, 2008Date of Patent: April 3, 2012Assignee: Samsung SDI Co., Ltd.Inventors: Han-su Kim, Dong-min Im, Young-su Chung
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Patent number: 8053110Abstract: A surface treated anode and a lithium battery using the same are provided. The surface treated anode includes a current collector, and an anode active material layer formed on the current collector. The anode active material layer is treated with an amine group containing compound.Type: GrantFiled: March 25, 2008Date of Patent: November 8, 2011Assignee: Samsung SDI Co., Ltd.Inventors: Gue-sung Kim, Dong-min Im, Seok-gwang Doo, Young-su Chung
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Patent number: 7964908Abstract: In one aspect, a memory cell includes a plurality of dielectric layers located within a charge storage gate structure. At least one of the dielectric layers includes an dielectric material including oxygen, and nano regions including oxygen embedded in the dielectric material, where an oxygen concentration of the dielectric material is the greater than an oxygen concentration of the nano regions. In another aspect, at least one of the dielectric layers includes a dielectric material and nano regions embedded in the dielectric material, where an atomic composition of the dielectric material is the same as the atomic composition of the nano regions, and a density of the dielectric material is the greater than a density of the nano regions.Type: GrantFiled: April 29, 2008Date of Patent: June 21, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-Jung Kim, Young-Sun Kim, Se-Hoon Oh, Eun-Ha Lee, Young-Su Chung
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Patent number: 7919820Abstract: Example embodiments provide a complementary metal-oxide semiconductor (CMOS) semiconductor device and a method of fabricating the CMOS semiconductor device. The CMOS semiconductor device may include gates in the nMOS and pMOS areas, polycrystalline silicon (poly-Si) capping layers, metal nitride layers underneath the poly-Si capping layers, and a gate insulating layer underneath the gate. The metal nitride layers of the nMOS and pMOS areas may be formed of the same type of material and may have different work functions. Since a metal gate is formed of identical types of metal nitride layers, a process may be simplified, yield may be increased, and a higher-performance CMOS semiconductor device may be obtained.Type: GrantFiled: January 10, 2008Date of Patent: April 5, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Young-su Chung, Hyung-suk Jung, Sung Heo, Hion-suck Baik
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Publication number: 20090317663Abstract: Provided is a magnetic recording medium. The magnetic recording medium includes a substrate, a recording layer disposed on the substrate for magnetic recording, and a carbon protection layer, which includes a carbon layer and a blocking layer disposed in the carbon layer to block infiltration of external impurities, disposed on the recording layer. Since the blocking layer is disposed in the carbon layer, a thickness of the carbon protection layer can be reduced while a sufficient hardness to protect the recording layer can be ensured, and moreover, a softness of the surface of the carbon protection layer can be improved.Type: ApplicationFiled: June 16, 2009Publication date: December 24, 2009Applicant: Samsung Electronics Co., LtdInventors: Sok-hyun KONG, Hyung-ik LEE, Hoo-san LEE, Young-su CHUNG, Seong-yong YOON
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Patent number: 7633087Abstract: A semiconductor thin film using a self-assembled monolayer (SAM) and a method for producing the semiconductor thin film are provided. According to the semiconductor thin film, a uniform inorganic seed layer is formed by using the self-assembled monolayer so that the adhesion between an insulating layer and a semiconductor layer is enhanced and thus the surface tension is reduced, thereby allowing the semiconductor thin film to have high quality without defects.Type: GrantFiled: May 3, 2006Date of Patent: December 15, 2009Assignee: Samsung Corning Precision Glass Co., Ltd.Inventors: Hyeon Jin Shin, Young Su Chung, Hyun Dam Jeong, Sang Heon Hyun, Jong Baek Seon
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Publication number: 20090053606Abstract: A surface treated anode and a lithium battery using the same are provided. The surface treated anode includes a current collector, and an anode active material layer formed on the current collector. The anode active material layer is treated with an amine group containing compound.Type: ApplicationFiled: March 25, 2008Publication date: February 26, 2009Applicant: Samsung SDI Co., Ltd.Inventors: GUE-SUNG KIM, Dong-min Im, Seok-Gwang Doo, Young-su Chung
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Publication number: 20080265310Abstract: In one aspect, a memory cell includes a plurality of dielectric layers located within a charge storage gate structure. At least one of the dielectric layers includes an dielectric material including oxygen, and nano regions including oxygen embedded in the dielectric material, where an oxygen concentration of the dielectric material is the greater than an oxygen concentration of the nano regions. In another aspect, at least one of the dielectric layers includes a dielectric material and nano regions embedded in the dielectric material, where an atomic composition of the dielectric material is the same as the atomic composition of the nano regions, and a density of the dielectric material is the greater than a density of the nano regions.Type: ApplicationFiled: April 29, 2008Publication date: October 30, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun-Jung Kim, Young-Sun Kim, Se-Hoon Oh, Eun-Ha Lee, Young-Su Chung