Abstract: A semiconductor chip includes a detection circuit configured to generate a discharge signal that is enabled when a voltage level of an external voltage is greater than a first set level and configured to generate a voltage control signal that is enabled when an output voltage is generated to have a voltage level of a ground voltage in a test mode, a charge discharge circuit configured to discharge charges of an output node that is included in a driving circuit when the discharge signal is enabled, and the driving circuit configured to generate the output voltage the voltage level of which rises up to a second set level by supplying charges from the external voltage to the output node in response to a driving signal a voltage level of which is decreased during an interval in which the voltage control signal is enabled.

Abstract: A reference voltage generation circuit may include: a first reference current path formed through a first node and a first transistor; a second reference current path formed through a second node and a second transistor; a first feedback loop configured to feed a first current back to the first and second reference current paths such that voltage levels of the first and second nodes are kept the same; and a second feedback loop configured to control the currents flowing through the first and second transistors according to a second current.

Abstract: A reference voltage generation circuit may include: a first reference current path formed through a first node and a first transistor; a second reference current path formed through a second node and a second transistor; a first feedback loop configured to feed a first current back to the first and second reference current paths such that voltage levels of the first and second nodes are kept the same; and a second feedback loop configured to control the currents flowing through the first and second transistors according to a second current.

Abstract: A data storage apparatus includes storage, and a controller including an internal voltage trimming circuit and controlling the storage in response to a request from a host. The trimming circuit may include an integral circuit sampling a difference between a test voltage output by a device under test and a reference voltage, generating an integral signal by integrating a sampled signal, and including an offset cancellation unit cancelling an offset from the sampled signal, a comparison circuit generating a comparison signal by comparing the integral signal with the reference voltage, a code generation circuit receiving an initial trimming code and generating preliminary trimming codes by increasing or decreasing the initial trimming code in response to the comparison signal, and a code average signal generation circuit generating the final trimming code by averaging the preliminary trimming codes for a given time and provide the final trimming code to the storage.

Abstract: A data storage apparatus includes storage, and a controller including an internal voltage trimming circuit and controlling the storage in response to a request from a host. The trimming circuit may include an integral circuit sampling a difference between a test voltage output by a device under test and a reference voltage, generating an integral signal by integrating a sampled signal, and including an offset cancellation unit cancelling an offset from the sampled signal, a comparison circuit generating a comparison signal by comparing the integral signal with the reference voltage, a code generation circuit receiving an initial trimming code and generating preliminary trimming codes by increasing or decreasing the initial trimming code in response to the comparison signal, and a code average signal generation circuit generating the final trimming code is by averaging the preliminary trimming codes for a given time and provide the final trimming code to the storage.

Abstract: There are provided a signal generation circuit and a semiconductor memory device including the same. The signal generation circuit includes: a signal input component configured to generate a first internal output signal and a second internal output signal in response to an input signal, and to adjust potential levels of the first internal output signal and the second internal output signal in response to an output signal; and a signal output component configured to generate the output signal in response to the first internal output signal and the second internal output signal.

Abstract: There are provided a signal generation circuit and a semiconductor memory device including the same. The signal generation circuit includes: a signal input component configured to generate a first internal output signal and a second internal output signal in response to an input signal, and to adjust potential levels of the first internal output signal and the second internal output signal in response to an output signal; and a signal output component configured to generate the output signal in response to the first internal output signal and the second internal output signal.

Abstract: Provided herein is temperature sensing circuit. The temperature sensing circuit may include a bandgap voltage generation circuit configured to generate first to third reference voltages independent of temperature change, a temperature compensation circuit configured to output a compensation voltage based on a temperature depending on the first reference voltage, a fixed voltage generation circuit configured to generate fixed voltages independent of the temperature change depending on the second and third reference voltages, and a converter configured to output a temperature code in response to the compensation voltage and the fixed voltages.

Abstract: A voltage generator includes a first voltage generation unit and a second voltage generation unit suitable for generating a second power supply voltage using a first power supply voltage, and being selectively driven, and a control signal generation unit suitable for activating the first voltage generation unit until the second power supply voltage reaches a specific level and activating the second voltage generation unit after the second power supply voltage reaches the specific level. The first voltage generation unit has less driving ability than the second voltage generation unit.

Abstract: Disclosed are a method and apparatus for controlling a booster circuit such that maximum power is extracted from a power supply while power consumption for monitoring power generated by the power supply is reduced, and an apparatus for extracting maximum power by using the method and apparatus for controlling a booster circuit.

Abstract: A sensing buffer, or peripheral circuit or memory device may be provided. The sensing buffer may be configured to maintain a predetermined current according to a first current regardless of an external power supply and/or a temperature.

Abstract: A sensing buffer, or peripheral circuit or memory device may be provided. The sensing buffer may be configured to maintain a predetermined current according to a first current regardless of an external power supply and/or a temperature.

Abstract: A voltage generator includes a first voltage generation unit and a second voltage generation unit suitable for generating a second power supply voltage using a first power supply voltage, and being selectively driven, and a control signal generation unit suitable for activating the first voltage generation unit until the second power supply voltage reaches a specific level and activating the second voltage generation unit after the second power supply voltage reaches the specific level. The first voltage generation unit has less driving ability than the second voltage generation unit.

Abstract: Disclosed are a method and apparatus for controlling a booster circuit such that maximum power is extracted from a power supply while power consumption for monitoring power generated by the power supply is reduced, and an apparatus for extracting maximum power by using the method and apparatus for controlling a booster circuit.

Abstract: There is provided a linear amplifier capable of suppressing a reduction in bandwidth and reducing a ripple voltage by using a source follower and a local feedback loop. The linear amplifier includes an amplifier amplifying an input signal according to a difference in signal level between the input signal and a feedback signal, and a buffer buffering a signal amplified in the amplifier by a source follow method, suppressing a reduction in bandwidth of the signal, outputting the signal, and providing the bufferred signal to the amplifier as the feedback signal.

Abstract: There is provided a linear amplifier capable of suppressing a reduction in bandwidth and reducing a ripple voltage by using a source follower and a local feedback loop. The linear amplifier includes an amplifier amplifying an input signal according to a difference in signal level between the input signal and a feedback signal, and a buffer buffering a signal amplified in the amplifier by a source follow method, suppressing a reduction in bandwidth of the signal, outputting the signal, and providing the buffered signal to the amplifier as the feedback signal.