Abstract: An electrostatic chuck unit includes: a first plate having a first surface and a second surface facing each other and a first hole extending from the first surface to the second surface; a second plate on the first surface of the first plate and having a groove corresponding to the first hole; a coupling bolt inserted into the first hole and the groove; and a height adjusting member spaced apart from the coupling bolt in a plan view.

Abstract: A deposition apparatus includes: a support module having a plurality of support parts coupled to a target substrate; a base substrate coupled to the support module; a connection member for connecting the plurality of support parts to the base substrate; and a mask assembly configured to mask a deposition material provided to the target substrate. The support module further includes position control parts, which control the plurality of support parts to be movable along a direction axis perpendicular to a major surface of each of the support parts, respectively.

Abstract: In a general aspect, an electronic device assembly includes a substrate arranged in a plane. The substrate has a first side and a second side, the second side being opposite the first side. The assembly also includes a plurality of semiconductor die disposed on the first side of the substrate and at least one signal pin. The at least one signal pin includes a proximal end portion coupled with the first side of the substrate, a distal end portion, and a medial portion disposed between the proximal end portion and the distal end portion. The medial portion is pre-molded in a molding compound, the proximal end portion and the distal end portion exclude the molding compound. The at least one signal pin is arranged along a longitudinal axis that is orthogonal to the plane of the substrate.

Abstract: Implementations of a semiconductor package may include one or more semiconductor die directly coupled to only a direct leadframe attach (DLA) leadframe including two or more leads; and a coating covering the one or more semiconductor die and the DLA leadframe where when the semiconductor package is coupled into an immersion cooling enclosure, the coating may be in contact with a dielectric coolant while the two or more leads extend out of the immersion cooling enclosure.

Abstract: A salicide treatment is performed on a common source line to reduce surface resistance and contact resistance, thereby improving a cell current characteristic. Therefore, a chip can be reduced in size and chips per wafer can be increased, thereby achieving high yield. In addition, it is possible to overcome the structural limitation of the flash cell when the semiconductor memory device is highly integrated and shrunken.

Abstract: A salicide treatment is performed on a common source line to reduce surface resistance and contact resistance, thereby improving a cell current characteristic. Therefore, a chip can be reduced in size and chips per wafer can be increased, thereby achieving high yield. In addition, it is possible to overcome the structural limitation of the flash cell when the semiconductor memory device is highly integrated and shrunken.