Patents by Inventor Young-sun Koh

Young-sun Koh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6717231
    Abstract: Methods of forming trench isolation regions include the steps of forming a semiconductor substrate having a trench therein and a masking layer thereon extending adjacent the trench. The masking layer may comprise silicon nitride. A recess-inhibiting layer is then formed on a sidewall of the trench and on a sidewall of the masking layer. Next, a stress-relief layer is formed on the recess-inhibiting layer. This stress-relief layer extends opposite the sidewall of the trench and opposite the sidewall of the masking layer and may comprise silicon nitride. The trench is then filled with a trench isolation layer. A sequence of planarization or etch-back steps are then performed to remove the masking layer and also align an upper surface of the trench isolation layer with a surface of the substrate. At least a portion of the masking layer is removed using a first etchant (e.g.
    Type: Grant
    Filed: August 20, 2002
    Date of Patent: April 6, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-eui Kim, Keum-joo Lee, In-seak Hwang, Young-sun Koh, Dong-ho Ahn, Moon-han Park, Tai-su Park
  • Publication number: 20030038334
    Abstract: Methods of forming trench isolation regions include the steps of forming a semiconductor substrate having a trench therein and a masking layer thereon extending adjacent the trench. The masking layer may comprise silicon nitride. A recess-inhibiting layer is then formed on a sidewall of the trench and on a sidewall of the masking layer. Next, a stress-relief layer is formed on the recess-inhibiting layer. This stress-relief layer extends opposite the sidewall of the trench and opposite the sidewall of the masking layer and may comprise silicon nitride. The trench is then filled with a trench isolation layer. A sequence of planarization or etch-back steps are then performed to remove the masking layer and also align an upper surface of the trench isolation layer with a surface of the substrate. At least a portion of the masking layer is removed using a first etchant (e.g.
    Type: Application
    Filed: August 20, 2002
    Publication date: February 27, 2003
    Inventors: Sung-eui Kim, Keum-joo Lee, In-seak Hwang, Young-sun Koh, Dong-ho Ahn, Moon-han Park, Tai-su Park
  • Patent number: 6461937
    Abstract: Methods of forming trench isolation regions include the steps of forming a semiconductor substrate having a trench therein and a masking layer thereon extending adjacent the trench. The masking layer may comprise silicon nitride. A recess-inhibiting layer is then formed on a sidewall of the trench and on a sidewall of the masking layer. Next, a stress-relief layer is formed on the recess-inhibiting layer. This stress-relief layer extends opposite the sidewall of the trench and opposite the sidewall of the masking layer and may comprise silicon nitride. The trench is then filled with a trench isolation layer. A sequence of planarization or etch-back steps are then performed to remove the masking layer and also align an upper surface of the trench isolation layer with a surface of the substrate. At least a portion of the masking layer is removed using a first etchant (e.g.
    Type: Grant
    Filed: January 7, 2000
    Date of Patent: October 8, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-eui Kim, Keum-joo Lee, In-seak Hwang, Young-sun Koh, Dong-ho Ahn, Moon-han Park, Tai-su Park