Abstract: A memory system and an operating method thereof include: at least a CPU configured to generate a special command; at least a PCIe link coupled with the CPU, wherein the PCIe link includes at least a PCIe switch; and a plurality of memory devices connected with the PCIe switch, wherein each of the plurality of memory devices includes a memory controller, an operational mode switch, and a plurality of memory components, and the operational mode switch is configured to perform a loopback from the memory controller corresponding to the special command at loopback operational mode.

Abstract: A memory system and an operating method thereof include: at least a CPU including multiple CPU cores, wherein the multiple CPU cores include reserved CPU cores and host CPU cores; at least a PCIe link coupled with the CPU, wherein the PCIe link includes at least a PCIe switch and a plurality of memory devices; and the plurality of memory devices coupled with the host CPU cores through respective workload threads and interrupt handlers, wherein the workload threads and interrupt handlers of each of the host CPU cores are configured to be optimized, the host CPU cores are isolated for the optimized workloads threads and interrupt handlers, and the workload threads and interrupt handlers are executed at the host CPU cores coupled thereto.

Abstract: Disclosed is a method of copying data between open-channel solid state drives (SSDs), the method including transmitting, by a host, a read command to a source SSD, performing, by the source SSD, a read operation on data stored in the source SSD, in response to the read command, specifying, by the source SSD, an address of a data buffer of a destination SSD, in response to the read command, copying, by the source SSD, the stored data to the specified address of the data buffer, and storing, by the destination SSD, the data copied from the source SSD.

Abstract: Disclosed is a method of transceiving data using a physical page address (PPA) command on an open-channel solid state drive (SSD), the method including transmitting, by a host, a PPA command to a controller using a submission queue, and performing, by the controller, an operation based on the PPA command, wherein the PPA command includes an operation code (Opcode) to operate the controller and a PPA list for the controller to perform the Opcode on a memory, and the PPA list includes at least one PPA and bitmap information related to the at least one PPA.

Abstract: A memory system and an operating method thereof include: at least a CPU configured to generate a special command; at least a PCIe link coupled with the CPU, wherein the PCIe link includes at least a PCIe switch; and a plurality of memory devices connected with the PCIe switch, wherein each of the plurality of memory devices includes a memory controller, an operational mode switch, and a plurality of memory components, and the operational mode switch is configured to perform a loopback from the memory controller corresponding to the special command at loopback operational mode.

Abstract: A memory system and an operating method thereof include: at least a CPU including multiple CPU cores, wherein the multiple CPU cores include reserved CPU cores and host CPU cores; at least a PCIe link coupled with the CPU, wherein the PCIe link includes at least a PCIe switch and a plurality of memory devices; and the plurality of memory devices coupled with the host CPU cores through respective workload threads and interrupt handlers, wherein the workload threads and interrupt handlers of each of the host CPU cores are configured to be optimized, the host CPU cores are isolated for the optimized workloads threads and interrupt handlers, and the workload threads and interrupt handlers are executed at the host CPU cores coupled thereto.

Abstract: Disclosed is a method of copying data between open-channel solid state drives (SSDs), the method including transmitting, by a host, a read command to a source SSD, performing, by the source SSD, a read operation on data stored in the source SSD, in response to the read command, specifying, by the source SSD, an address of a data buffer of a destination SSD, in response to the read command, copying, by the source SSD, the stored data to the specified address of the data buffer, and storing, by the destination SSD, the data copied from the source SSD.

Abstract: Disclosed is a method of transceiving data using a physical page address (PPA) command on an open-channel solid state drive (SSD), the method including transmitting, by a host, a PPA command to a controller using a submission queue, and performing, by the controller, an operation based on the PPA command, wherein the PPA command includes an operation code (Opcode) to operate the controller and a PPA list for the controller to perform the Opcode on a memory, and the PPA list includes at least one PPA and bitmap information related to the at least one PPA.

Abstract: Disclosed is a method of filling up data on an open-channel solid state drive (SSD), the method including transmitting information related to a word line to be filled up in response to a geometry command from a host, receiving a word line fill up command from the host based on the information, generating a command to fill up a first word line of a NAND flash memory with pre-defined data in response to the word line fill up command, transmitting the command to a NAND interface (IF) control logic of the controller, generating, by the NAND IF control logic, the pre-defined data in response to the command, transmitting, by the NAND IF control logic, the pre-defined data to a control logic of the NAND flash memory, and filling up, by the control logic, the first word line with the pre-defined data.

Abstract: A memory system and an operating method thereof include: at least a CPU configured to generate a special command; at least a PCIe link coupled with the CPU, wherein the PCIe link includes at least a PCIe switch; and a plurality of memory devices connected with the PCIe switch, wherein each of the plurality of memory devices includes a memory controller, an operational mode switch, and a plurality of memory components, and the operational mode switch is configured to perform a loopback from the memory controller corresponding to the special command at loopback operational mode.

Abstract: A memory system and an operating method thereof include: at least a CPU including multiple CPU cores, wherein the multiple CPU cores include reserved CPU cores and host CPU cores; at least a PCIe link coupled with the CPU, wherein the PCIe link includes at least a PCIe switch and a plurality of memory devices; and the plurality of memory devices coupled with the host CPU cores through respective workload threads and interrupt handlers, wherein the workload threads and interrupt handlers of each of the host CPU cores are configured to be optimized, the host CPU cores are isolated for the optimized workloads threads and interrupt handlers, and the workload threads and interrupt handlers are executed at the host CPU cores coupled thereto.

Abstract: A memory system and an operating method thereof include: at least a CPU including multiple CPU cores, wherein the multiple CPU cores include reserved CPU cores and host CPU cores; at least a PCIe link coupled with the CPU, wherein the PCIe link includes at least a PCIe switch and a plurality of memory devices; and the plurality of memory devices coupled with the host CPU cores through respective workload threads and interrupt handlers, wherein the workload threads and interrupt handlers of each of the host CPU cores are configured to be optimized, the host CPU cores are isolated for the optimized workloads threads and interrupt handlers, and the workload threads and interrupt handlers are executed at the host CPU cores coupled thereto.

Abstract: A memory system and an operating method thereof include: at least a CPU configured to generate a special command; at least a PCIe link coupled with the CPU, wherein the PCIe link includes at least a PCIe switch; and a plurality of memory devices connected with the PCIe switch, wherein each of the plurality of memory devices includes a memory controller, an operational mode switch, and a plurality of memory components, and the operational mode switch is configured to perform a loopback from the memory controller corresponding to the special command at loopback operational mode.

Abstract: A bootable volatile memory device comprises a volatile memory area configured to be written to and read from by a host processor, a boot code area configured to store bootstrap code before a boot procedure is performed by the host processor, a first chip select terminal configured to output a signal used as a chip select signal where the host processor performs the boot procedure by reading the bootstrap code from the boot code area, and a second chip select terminal configured to output a signal used as a chip select signal where the host processor writes and reads data to and from the volatile memory area.

Abstract: A bootable volatile memory device comprises a volatile memory area configured to be written to and read from by a host processor, a boot code area configured to store bootstrap code before a boot procedure is performed by the host processor, a first chip select terminal configured to output a signal used as a chip select signal where the host processor performs the boot procedure by reading the bootstrap code from the boot code area, and a second chip select terminal configured to output a signal used as a chip select signal where the host processor writes and reads data to and from the volatile memory area.