Abstract: A programmable timer circuit which is integrated into an application specific integrated circuit includes a programmable timer counter. The programmable timer counter receives count data which is written to registers of the integrated circuit and is caused to initiate a count until that count is reached in response to clock signal. A programmable microprocessor is provided for controlling the programmable timer circuit and reading count data and mode data from non-volatile memory units in response to the microprocessor's programming and writing the count data and mode data into the registers of the application specific integrated circuit. In response to the mode data the programmable timer circuit assumes either a one shot mode or a continuos mode when the programmable timer.

Abstract: A programmable timer circuit is comprised of a programmable timer counter for receiving a count and for counting to the count. A clock signal for driving the timer counter which timer counter generates a signal representative of the count. A microprocessor generates count data in response to programming of the microprocessor. Timer data register receive the count from microprocessor. A first gate is provided having an enabled mode and an non-enabled mode for enabling loading of the timer data from the timer data register to the timer counter input only in the enabled mode. A monitoring circuit is provided for monitoring the timer count and enabling the gate mean to the enabled mode only when the timer has time-out.

Abstract: A data verification system including a circuit verifies that unlocking data generated by a microprocessor to be written into the ASIC before a memory write is valid. The microprocessor is programmed to generate an ASIC address when unlocking data is to be written to the ASIC and to encrypt and decrypt that data. The verifying circuit unit receives the encrypted data and decrypts the encrypted data and compares the decrypted data with the encrypted data. The verifying circuit generating an enable signal only if the comparison is true. An address decoding unit is provided for receiving the memory address signal and causing a memory write enable signal to be generated for the memory unit only if the verifying circuit unit has generated an enable signal. Registers unit in communication with the data bus and the verifying circuit unit are provided for writing decryption parameters in the register unit in accordance with the programming of the microprocessor during power-up of the microprocessor.