Abstract: Disclosed is a liquid crystal display panel. The liquid crystal display panel includes an active region formed at an upper surface thereof with a plurality of gate lines and data lines aligned in cross to each other, in order to display image data applied to the data lines, a plurality of gate pads formed at a first outside of the active region and connected to each of the gate lines, a plurality of data pads formed at a second outside of the active region and connected to each of the data lines, and a pair of anti-electrostatic thin film transistors formed at each gate pad and each data pad, respectively, in order to carry out functions of inner and outer ESDs and to transfer static electricity generated from a corresponding pad to an adjacent pad. Due to the anti-electrostatic thin film transistors formed at each pad, an extra space for forming additional EDSs is not necessary, thereby minimizing a space occupied by the ESDs and maximizing a space section of the liquid crystal display panel.

Abstract: The present invention relates to a liquid crystal display having no gate PCB and FPC. This comprises: a liquid crystal panel formed by an assemble an array substrate and a color filter substrate with a liquid crystal layer interposed therebetween; a plurality of source TCPs and gate TCPs, which are attached to a source and a gate of the liquid panel, respectively, and mounted with a gate driver IC and a source driver IC, respectively; a source PCB connected to the source TCPs and serving to apply a given driving signal to the source driver IC; a LOG formed on the liquid crystal panel such that a signal from the source PCB is applied to the gate driver IC via the gate TCPs; and transfers formed between the substrates at edges of the liquid crystal panel such that common voltage is applied to the color filter substrate. In this liquid crystal display, the LOG consists of gate driver IC-driving signal lines without having a common line for connecting the transfers with each other.

Abstract: Disclosed is a liquid crystal display panel. The liquid crystal display panel includes an active region formed at an upper surface thereof with a plurality of gate lines and data lines aligned in cross to each other, in order to display image data applied to the data lines, a plurality of gate pads formed at a first outside of the active region and connected to each of the gate lines, a plurality of data pads formed at a second outside of the active region and connected to each of the data lines, and a pair of anti-electrostatic thin film transistors formed at each gate pad and each data pad, respectively, in order to carry out functions of inner and outer ESDs and to transfer static electricity generated from a corresponding pad to an adjacent pad. Due to the anti-electrostatic thin film transistors formed at each pad, an extra space for forming additional EDSs is not necessary, thereby minimizing a space occupied by the ESDs and maximizing a space section of the liquid crystal display panel.

Abstract: The present invention relates to a liquid crystal display having no gate PCB and FPC. This comprises: a liquid crystal panel formed by an assemble an array substrate and a color filter substrate with a liquid crystal layer interposed therebetween; a plurality of source TCPs and gate TCPs, which are attached to a source and a gate of the liquid panel, respectively, and mounted with a gate driver IC and a source driver IC, respectively; a source PCB connected to the source TCPs and serving to apply a given driving signal to the source driver IC; a LOG formed on the liquid crystal panel such that a signal from the source PCB is applied to the gate driver IC via the gate TCPs; and transfers formed between the substrates at edges of the liquid crystal panel such that common voltage is applied to the color filter substrate. In this liquid crystal display, the LOG consists of gate driver IC-driving signal lines without having a common line for connecting the transfers with each other.

Abstract: Disclosed is a liquid crystal display device and a fabrication method thereof comprises a data PCB substrate having a data pad block and a gate PCB substrate having a gate pad block; a data dummy pad and a gate dummy pad formed on the data PCB substrate and on the gate PCB substrate, respectively; and a repair redundancy line formed on the gate pad block and the data pad block to form a redundancy line path between them.