Patents by Inventor Young-Yong Byun
Young-Yong Byun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11670559Abstract: A semiconductor device including a substrate including a chip region and an edge region; integrated circuit elements on the chip region; an interlayer insulating layer covering the integrated circuit elements; an interconnection structure on the interlayer insulating layer and having a side surface on the edge region; a first and second conductive pattern on the interconnection structure, the first and second conductive patterns being electrically connected to the interconnection structure; a first passivation layer covering the first and second conductive patterns and the side surface of the interconnection structure; and a second passivation layer on the first passivation layer, wherein the second passivation layer includes an insulating material different from the first passivation layer, and, between the first and second conductive patterns, the second passivation layer has a bottom surface that is located at a vertical level lower than a top surface of the first conductive pattern.Type: GrantFiled: March 19, 2021Date of Patent: June 6, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Minjung Choi, Jung-Hoon Han, Jiho Kim, Young-Yong Byun, Yeonjin Lee, Jihoon Chang
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Publication number: 20210305115Abstract: A semiconductor device including a substrate including a chip region and an edge region; integrated circuit elements on the chip region; an interlayer insulating layer covering the integrated circuit elements; an interconnection structure on the interlayer insulating layer and having a side surface on the edge region; a first and second conductive pattern on the interconnection structure, the first and second conductive patterns being electrically connected to the interconnection structure; a first passivation layer covering the first and second conductive patterns and the side surface of the interconnection structure; and a second passivation layer on the first passivation layer, wherein the second passivation layer includes an insulating material different from the first passivation layer, and, between the first and second conductive patterns, the second passivation layer has a bottom surface that is located at a vertical level lower than a top surface of the first conductive pattern.Type: ApplicationFiled: March 19, 2021Publication date: September 30, 2021Inventors: Minjung CHOI, Jung-Hoon HAN, Jiho KIM, Young-Yong BYUN, Yeonjin LEE, Jihoon CHANG
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Patent number: 10127102Abstract: A semiconductor memory device includes a memory cell array, a control logic circuit, an error correction circuit and a first path selection circuit. The memory cell array includes a plurality of bank arrays. The control logic circuit controls access to the memory cell array and generates a density mode signal based on a command. The first path selection circuit selectively provides write data to the error correction circuit.Type: GrantFiled: August 5, 2016Date of Patent: November 13, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ye-Sin Ryu, Hoi-Ju Chung, Sang-Uhn Cha, Young-Yong Byun, Seong-Jin Jang
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Patent number: 10062427Abstract: Provided is a semiconductor memory device for controlling a refresh operation of redundancy memory cells. The semiconductor memory device may include normal memory cells and redundancy memory cells that are used to repair normal memory cell(s) to which a defective cell is connected, and an error-correction code (ECC) memory cell row that stores parity bits for controlling the defective cell. Memory cells on the normal memory cell rows are refreshed during a first refresh cycle. Other memory cells on, such as redundancy memory cell rows, an edge memory cell row that is adjacent to the redundancy memory cell row(s) from among the normal memory cell rows, and/or the ECC memory cell row may be refreshed during a second refresh cycle that is different from the first refresh cycle.Type: GrantFiled: May 27, 2015Date of Patent: August 28, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Whi-Young Bae, Young-Sik Kim, Young-Yong Byun
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Patent number: 9824946Abstract: A method of manufacturing a semiconductor chip from a wafer having a test architecture includes forming a plurality of dies on a wafer, each of the plurality of dies including a semiconductor device, forming at least two common pads commonly coupled to the dies, the at least two common pads being formed in a scribe lane, the scribe lane distinguishing the dies with respect to each other, and simultaneously testing the semiconductor devices at a wafer level, using the at least two common pads.Type: GrantFiled: August 9, 2016Date of Patent: November 21, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Yong Byun, Ho-Sung Song, Chi-Wook Kim
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Publication number: 20170170081Abstract: A method of manufacturing a semiconductor chip from a wafer having a test architecture includes forming a plurality of dies on a wafer, each of the plurality of dies including a semiconductor device, forming at least two common pads commonly coupled to the dies, the at least two common pads being formed in a scribe lane, the scribe lane distinguishing the dies with respect to each other, and simultaneously testing the semiconductor devices at a wafer level, using the at least two common pads.Type: ApplicationFiled: August 9, 2016Publication date: June 15, 2017Inventors: Young-Yong BYUN, Ho-Sung SONG, Chi-Wook KIM
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Publication number: 20170083401Abstract: A semiconductor memory device includes a memory cell array, a control logic circuit, an error correction circuit and a first path selection circuit. The memory cell array includes a plurality of bank arrays. The control logic circuit controls access to the memory cell array and generates a density mode signal based on a command. The first path selection circuit selectively provides write data to the error correction circuit.Type: ApplicationFiled: August 5, 2016Publication date: March 23, 2017Inventors: Ye-sin Ryu, Hoi-Ju CHUNG, Sang-Uhn CHA, Young-Yong BYUN, Seong-Jin JANG
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Patent number: 9601179Abstract: A semiconductor memory device may include a memory cell array, a first decoder and a second decoder. The memory cell array includes a plurality of memory cell rows. The first decoder is configured to select a first number of memory cell rows of the plurality of memory cell rows based on a selected refresh row address of a set of row addresses. The second decoder is configured to select a second number of memory cell rows of the plurality of memory cell rows based on the selected refresh row address. A total number of the first number and the second number is varied in response to the selected refresh row address.Type: GrantFiled: May 27, 2015Date of Patent: March 21, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Yong Byun, Whi-Young Bae
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Publication number: 20160027492Abstract: A semiconductor memory device may include a memory cell array, a first decoder and a second decoder. The memory cell array includes a plurality of memory cell rows. The first decoder is configured to select a first number of memory cell rows of the plurality of memory cell rows based on a selected refresh row address of a set of row addresses. The second decoder is configured to select a second number of memory cell rows of the plurality of memory cell rows based on the selected refresh row address. A total number of the first number and the second number is varied in response to the selected refresh row address.Type: ApplicationFiled: May 27, 2015Publication date: January 28, 2016Inventors: Young-Yong BYUN, Whi-Young BAE
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Publication number: 20160005452Abstract: Provided is a semiconductor memory device for controlling a refresh operation of redundancy memory cells. The semiconductor memory device may include normal memory cells and redundancy memory cells that are used to repair normal memory cell(s) to which a defective cell is connected, and an error-correction code (ECC) memory cell row that stores parity bits for controlling the defective cell. Memory cells on the normal memory cell rows are refreshed during a first refresh cycle. Other memory cells on, such as redundancy memory cell rows, an edge memory cell row that is adjacent to the redundancy memory cell row(s) from among the normal memory cell rows, and/or the ECC memory cell row may be refreshed during a second refresh cycle that is different from the first refresh cycle.Type: ApplicationFiled: May 27, 2015Publication date: January 7, 2016Inventors: Whi-Young BAE, Young-Sik KIM, Young-Yong BYUN
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Patent number: 9087558Abstract: A semiconductor device may comprise a first bit line, a second bit line, a memory cell connected to the first bit line, a bit line sense amplifier circuit and a control circuit. The bit line sense amplifier circuit may be coupled to the memory cell. The bit line sense amplifier circuit may include a first inverter having an input node coupled to the first bit line and an output node coupled to the second bit line, and a second inverter having an input node coupled to the second bit line and an output node coupled to the first bit line. The control circuit may be configured to activate the first inverter without activating the second inverter during a first time period and to activate the first inverter and the second inverter at the same time during a second time period after the first time period.Type: GrantFiled: October 22, 2013Date of Patent: July 21, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Hak Shin, Yong-Sang Park, Young-Yong Byun, In-Chul Jeong
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Patent number: 8873277Abstract: A semiconductor memory device includes a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers.Type: GrantFiled: October 10, 2012Date of Patent: October 28, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hyeoung-won Seo, Soo-ho Shin, Won-woo Lee, Jeong-soo Park, Young-yong Byun, Seong-jin Jang, Sang-woong Shin
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Publication number: 20140233336Abstract: A semiconductor device may comprise a first bit line, a second bit line, a memory cell connected to the first bit line, a bit line sense amplifier circuit and a control circuit. The bit line sense amplifier circuit may be coupled to the memory cell. The bit line sense amplifier circuit may include a first inverter having an input node coupled to the first bit line and an output node coupled to the second bit line, and a second inverter having an input node coupled to the second bit line and an output node coupled to the first bit line. The control circuit may be configured to activate the first inverter without activating the second inverter during a first time period and to activate the first inverter and the second inverter at the same time during a second time period after the first time period.Type: ApplicationFiled: October 22, 2013Publication date: August 21, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Dong-Hak SHIN, Yong-Sang PARK, Young-Yong BYUN, In-Chul JEONG
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Patent number: 8310859Abstract: A semiconductor memory device includes a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers.Type: GrantFiled: September 30, 2009Date of Patent: November 13, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Hyeoung-won Seo, Soo-ho Shin, Won-woo Lee, Jeong-soo Park, Young-yong Byun, Seong-jin Jang, Sang-woong Shin
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Patent number: 8228704Abstract: A semiconductor chip package and a semiconductor chip fabricating method are provided. A semiconductor chip package comprises at least two semiconductor chips having a stacked configuration, the semiconductor chips at least one of: sharing DC signals of DC generating circuits provided by one of the semiconductor chips; and sharing a DLL clock signal of a DLL circuit provided by the semiconductor chip having the DC generating circuits or provided by another semiconductor chip. Power consumption can be reduced, and sharing a DLL clock is valid. In addition, a stabilized DC supply can be guaranteed and an increase for level trimming range and productivity can be improved.Type: GrantFiled: February 26, 2008Date of Patent: July 24, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Chul-Hwan Choo, Hi-Choon Lee, Young-Yong Byun
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Patent number: 8228755Abstract: A word line driving circuit includes an address decoding signal generating unit and a word line voltage supply unit. The address decoding signal generating unit includes inverter chain receiving and delaying a first address decoding signal and outputting the delayed first address decoding signal. The word line voltage supply unit includes a pull-up driver that supplies the delayed first address signal to a selected word line in response to a second address decoding signal. The inverter chain includes an NMOS transistor outputting the delayed first address signal and a source terminal of the NMOS transistor receives a set voltage that is higher than a ground voltage and lower than a high voltage.Type: GrantFiled: January 28, 2010Date of Patent: July 24, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Ho Park, Young-Yong Byun, Yamada Satoru
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Publication number: 20100202241Abstract: A word line driving circuit includes an address decoding signal generating unit and a word line voltage supply unit. The address decoding signal generating unit includes inverter chain receiving and delaying a first address decoding signal and outputting the delayed first address decoding signal. The word line voltage supply unit includes a pull-up driver that supplies the delayed first address signal to a selected word line in response to a second address decoding signal. The inverter chain includes an NMOS transistor outputting the delayed first address signal and a source terminal of the NMOS transistor receives a set voltage that is higher than a ground voltage and lower than a high voltage.Type: ApplicationFiled: January 28, 2010Publication date: August 12, 2010Inventors: Hyun-Ho PARK, Young-Yong BYUN, Yamada SATORU
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Patent number: 7755958Abstract: A semiconductor memory device and method thereof are provided. The example semiconductor memory device may include a plurality of comparators receiving output data signals from each of a plurality of sub-array blocks, comparing the output data signals from each of the plurality of sub-array blocks and outputting a plurality of comparison result signals and a test circuit receiving the plurality of comparison result signals from the plurality of comparators, respectively, the test circuit configured to selectively output one of a given one of the plurality of comparison result signals on a given data input/output pad and a given signal obtained by performing a logical operation on at least two of the plurality of comparison result signals on the given data input/output pad in response to a select signal.Type: GrantFiled: July 20, 2007Date of Patent: July 13, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Young-yong Byun, Hi-choon Lee
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Publication number: 20100080044Abstract: According to some of the inventive concepts, a semiconductor memory device may include a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers.Type: ApplicationFiled: September 30, 2009Publication date: April 1, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyeoung-won SEO, Young-yong BYUN, Seong-jin JANG, Sang-woong SHIN, Soo-ho SHIN, Won-woo LEE, Jeong-soo PARK
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Patent number: 7656207Abstract: Provided are a DLL circuit having a coarse lock time adaptive to a frequency band of an external clock signal and a semiconductor memory device having the DLL circuit. The DLL circuit includes a delay circuit, a replica circuit, and a phase detector. The phase detector generates a first comparison signal used by the delay circuit to delay an external clock signal in units of a first cell delay time or a second comparison signal used by the delay circuit to delay the external clock signal in units of a second cell delay time. The DLL circuit delays the external clock signal by the cell delay time adaptive to the frequency band of the external clock signal, and thus can perform an accurate and rapid coarse lock operation for the entire frequency band.Type: GrantFiled: January 16, 2008Date of Patent: February 2, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Young-yong Byun