Abstract: According to an embodiment, a buffer circuit comprises an operational amplifier configured to output an output voltage based on a voltage of a first output node and a second output node which vary in response to an input voltage of the operational amplifier; and a slew rate compensating circuit configured to receive the input voltage and the output voltage, generate a compensation voltage based on the input voltage, generate a compensation current based on the compensation voltage, and supply the compensation current to the first output node or the second output node.

Abstract: Provided is an offset compensating circuit that includes: an input stage circuit with first and second input circuits, a first multiplexer configured to activate one of the first second input circuits, a second multiplexer configured to change a polarity of an offset, and an offset trimming circuit configured to compensate the offset; an amplification stage circuit with a first current mirror, a second current mirror and a third multiplexer configured to change the polarity of the offset; an output stage circuit configured to receive voltages generated from the first current mirror and the second current mirror; and a switch configured to control a path connected to the output stage circuit or the input stage circuit.

Abstract: In one embodiment, the control integrated circuit includes a gate driver configured to selectively drive a plurality of gate lines associated with pixels in a display panel; a source driver configured to supply data to the display panel; and a controller configured to generate switch control signals for controlling a switch driver of the display panel, the switch driver for selectively supplying the data to a plurality of data lines. The controller is configured to control the gate driver and generate the switch control signals such that the plurality of gate lines are activated non-sequentially, and an order of pixels activated and associated with a same one of the plurality of data lines includes at least two pixels of a same color activated in sequence.

Abstract: A display driver circuit includes a source driver configured to output display data to data lines, a controller configured to control the source driver, based on a synchronization signal, and a frequency adjusting circuit configured to extend a first time interval of the synchronization signal from a first length to a second length, such that time interval in which the display data is not output to the data lines is extended, when second image data are not received from an external device during a reference time interval after first image data are received from the external device, and shorten the first time interval, from the second length to a third length, when an instruction is received from the external device after the first time interval is extended to the second length.

Abstract: A display driver circuit includes a source driver configured to output display data to data lines, a controller configured to control the source driver, based on a synchronization signal, and a frequency adjusting circuit configured to extend a first time interval of the synchronization signal from a first length to a second length, such that time interval in which the display data is not output to the data lines is extended, when second image data are not received from an external device during a reference time interval after first image data are received from the external device, and shorten the first time interval, from the second length to a third length, when an instruction is received from the external device after the first time interval is extended to the second length.

Abstract: A display device including a display panel and a driving circuit configured to drive the display panel may be provided. The display panel includes a plurality of gate lines, a plurality of data lines and a plurality of sub pixels connected to the plurality of gate lines and the plurality of data lines, respectively. The display panel has a zigzag connection structure in which RG sub pixel pairs included in a first odd-numbered row and RG sub pixel pairs included in a first even-numbered row adjacent to the first odd-numbered row are alternately connected to a first common gate line, and BG sub pixel pairs included in a second odd-numbered row and BG sub pixel pairs included in a second even-numbered row adjacent to the second odd-numbered row are alternately connected to a second common gate line.

Abstract: A display device including a display panel and a driving circuit configured to drive the display panel may be provided. The display panel includes a plurality of gate lines, a plurality of data lines and a plurality of sub pixels connected to the plurality of gate lines and the plurality of data lines, respectively.

Abstract: In one embodiment, the control integrated circuit includes a gate driver configured to selectively drive a plurality of gate lines associated with pixels in a display panel; a source driver configured to supply data to the display panel; and a controller configured to generate switch control signals for controlling a switch driver of the display panel, the switch driver for selectively supplying the data to a plurality of data lines. The controller is configured to control the gate driver and generate the switch control signals such that the plurality of gate lines are activated non-sequentially, and an order of pixels activated and associated with a same one of the plurality of data lines includes at least two pixels of a same color activated in sequence.

Abstract: A display driver includes a gamma voltage generation unit, a decoder, and a plurality of source amplifiers. The gamma voltage generation unit generates gamma reference voltages. The decoder transforms pixel data corresponding to received image information into data voltages using the gamma reference voltages. The plurality of source amplifiers outputs the data voltages to a display panel. The gamma voltage generation unit includes a first amplifier receiving a reference voltage and a voltage divider including a plurality of resistors and at least one first switch. The at least one first switch turns on or turns off a first connection between an output node of the first amplifier and the plurality of resistors depending on an operation mode. The voltage divider generates at least one first gamma reference voltage among the gamma reference voltages based on an output voltage of the first amplifier.

Abstract: A display driver includes a gamma voltage generation unit, a decoder, and a plurality of source amplifiers. The gamma voltage generation unit generates gamma reference voltages. The decoder transforms pixel data corresponding to received image information into data voltages using the gamma reference voltages. The plurality of source amplifiers outputs the data voltages to a display panel. The gamma voltage generation unit includes a first amplifier receiving a reference voltage and a voltage divider including a plurality of resistors and at least one first switch. The at least one first switch turns on or turns off a first connection between an output node of the first amplifier and the plurality of resistors depending on an operation mode. The voltage divider generates at least one first gamma reference voltage among the gamma reference voltages based on an output voltage of the first amplifier.

Abstract: The display device includes a driving circuit and a panel. The driving circuit is configured to generate a source output enable signal having at least one pulse during one horizontal scanning period in response to a mode signal and configured to generate a source driving signal by latching an image data in response to the source output enable signal. The driving circuit is further configured to generate an internal horizontal synchronization signal in response to the source output enable signal and configured to generate a gate driving signal in response to the internal horizontal synchronization signal. The panel is configured to display the image data in response to the gate driving signal and the source driving signal.

Abstract: The display device includes a driving circuit and a panel. The driving circuit is configured to generate a source output enable signal having at least one pulse during one horizontal scanning period in response to a mode signal and configured to generate a source driving signal by latching an image data in response to the source output enable signal. The driving circuit is further configured to generate an internal horizontal synchronization signal in response to the source output enable signal and configured to generate a gate driving signal in response to the internal horizontal synchronization signal. The panel is configured to display the image data in response to the gate driving signal and the source driving signal.