Patents by Inventor Young Chan Ko
Young Chan Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12148708Abstract: A semiconductor package including a core structure, in which a first and second semiconductor chips and passive components are embedded, a connection structure disposed on a first side of the core structure, and including a redistribution layer electrically connected to the first and second semiconductor chips and the passive components, and a metal pattern layer and a backside wiring layer disposed on a second side of the core structure opposing the first side, and spaced apart from each other. The core structure includes a first metal layer surrounding the first semiconductor chip, a second metal layer surrounding the first semiconductor chip, and the first metal layer, a third metal layer surrounding the second semiconductor chip, and a fourth metal layer surrounding the second semiconductor chip, the passive components, and the third metal layer, and each of the first to fourth metal layers is electrically connected to the metal pattern layer.Type: GrantFiled: May 1, 2023Date of Patent: November 19, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Koon Lee, Myung Sam Kang, Young Gwan Ko, Young Chan Ko, Chang Bae Lee
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Patent number: 11894310Abstract: A fan-out semiconductor package including a first redistribution layer; a first semiconductor chip on the first redistribution layer; an interconnector on the first redistribution layer and spaced apart from the first semiconductor chip; a molded layer covering the interconnector and side surfaces of the first semiconductor chip; and a second redistribution layer on the molded layer, wherein the interconnector includes a metal ball and is electrically connected to the first redistribution layer, the second redistribution layer includes a first line wiring, and a first via electrically connected to the first line wiring, the first via is connected to the interconnector, and a part of the first via is in the molded layer.Type: GrantFiled: March 8, 2021Date of Patent: February 6, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myung Sam Kang, Ki Ju Lee, Young Chan Ko, Jeong Seok Kim, Bong Ju Cho
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Publication number: 20230260919Abstract: A semiconductor package including a core structure, in which a first and second semiconductor chips and passive components are embedded, a connection structure disposed on a first side of the core structure, and including a redistribution layer electrically connected to the first and second semiconductor chips and the passive components, and a metal pattern layer and a backside wiring layer disposed on a second side of the core structure opposing the first side, and spaced apart from each other. The core structure includes a first metal layer surrounding the first semiconductor chip, a second metal layer surrounding the first semiconductor chip, and the first metal layer, a third metal layer surrounding the second semiconductor chip, and a fourth metal layer surrounding the second semiconductor chip, the passive components, and the third metal layer, and each of the first to fourth metal layers is electrically connected to the metal pattern layer.Type: ApplicationFiled: May 1, 2023Publication date: August 17, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Koon LEE, Myung Sam KANG, Young Gwan KO, Young Chan KO, Chang Bae LEE
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Patent number: 11676907Abstract: A method including forming a frame having an opening, forming a first metal layer, forming a first encapsulant, forming an insulation layer on the first metal layer, forming a first through-hole and a second through-hole penetrating the insulation layer and the first encapsulant, forming a second metal layer and a third metal layer, forming a second encapsulant, forming a first metal via and a second metal via penetrating the second encapsulant and a metal pattern layer on the second encapsulant, and forming a connection structure. The first metal layer and the second metal layer respectively are formed to extend to a surface of each of the first encapsulant and the frame, facing the metal pattern layer, and the first metal layer and the second metal layer are connected to the metal pattern layer through the first metal via and the second metal via having heights different from each other.Type: GrantFiled: June 21, 2021Date of Patent: June 13, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Koon Lee, Myung Sam Kang, Young Gwan Ko, Young Chan Ko, Chang Bae Lee
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Publication number: 20220037259Abstract: A fan-out semiconductor package including a first redistribution layer; a first semiconductor chip on the first redistribution layer; an interconnector on the first redistribution layer and spaced apart from the first semiconductor chip; a molded layer covering the interconnector and side surfaces of the first semiconductor chip; and a second redistribution layer on the molded layer, wherein the interconnector includes a metal ball and is electrically connected to the first redistribution layer, the second redistribution layer includes a first line wiring, and a first via electrically connected to the first line wiring, the first via is connected to the interconnector, and a part of the first via is in the molded layer.Type: ApplicationFiled: March 8, 2021Publication date: February 3, 2022Inventors: Myung Sam KANG, Ki Ju LEE, Young Chan KO, Jeong Seok KIM, Bong Ju CHO
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Publication number: 20210313276Abstract: A method including forming a frame having an opening, forming a first metal layer, forming a first encapsulant, forming an insulation layer on the first metal layer, forming a first through-hole and a second through-hole penetrating the insulation layer and the first encapsulant, forming a second metal layer and a third metal layer, forming a second encapsulant, forming a first metal via and a second metal via penetrating the second encapsulant and a metal pattern layer on the second encapsulant, and forming a connection structure. The first metal layer and the second metal layer respectively are formed to extend to a surface of each of the first encapsulant and the frame, facing the metal pattern layer, and the first metal layer and the second metal layer are connected to the metal pattern layer through the first metal via and the second metal via having heights different from each other.Type: ApplicationFiled: June 21, 2021Publication date: October 7, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Koon LEE, Myung Sam KANG, Young Gwan KO, Young Chan KO, Chang Bae LEE
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Patent number: 11062999Abstract: A semiconductor package includes a core structure having a first through-hole and including a frame having an opening, a passive component disposed in the opening, a first encapsulant covering the frame and the passive component, a first metal layer disposed on an inner surface of the first through-hole, and a second metal layer disposed on an inner surface of the opening; a first semiconductor chip disposed in the first through-hole and having a first connection pad; a second encapsulant covering the core structure and the first semiconductor chip; a connection structure disposed on the core structure and the first semiconductor chip and including a redistribution layer; and a metal pattern layer disposed on the second encapsulant. The first and second metal layers are connected to the metal pattern layer through first and second metal vias having heights different from each other.Type: GrantFiled: September 13, 2019Date of Patent: July 13, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Koon Lee, Myung Sam Kang, Young Gwan Ko, Young Chan Ko, Chang Bae Lee
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Patent number: 11037880Abstract: A semiconductor package includes a frame having first and second through-portions, first and second semiconductor chips, respectively in the first and second through-portions, each having a first surface, on which a connection pad is disposed, a first encapsulant covering at least a portion of the first and second semiconductor chips, a first connection member on the first and second semiconductor chips including a first redistribution layer electrically connected to the connection pads of the first and second semiconductor chips and a heat dissipation pattern layer, at least one passive component above the first semiconductor chip on the first connection member, and at least one heat dissipation structure above the second semiconductor chip on the first connection member and connected to the heat dissipation pattern layer.Type: GrantFiled: August 30, 2019Date of Patent: June 15, 2021Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Myung Sam Kang, Yong Koon Lee, Young Gwan Ko, Young Chan Ko, Moon Il Kim
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Publication number: 20200373244Abstract: A semiconductor package includes a frame having first and second through-portions, first and second semiconductor chips, respectively in the first and second through-portions, each having a first surface, on which a connection pad is disposed, a first encapsulant covering at least a portion of the first and second semiconductor chips, a first connection member on the first and second semiconductor chips including a first redistribution layer electrically connected to the connection pads of the first and second semiconductor chips and a heat dissipation pattern layer, at least one passive component above the first semiconductor chip on the first connection member, and at least one heat dissipation structure above the second semiconductor chip on the first connection member and connected to the heat dissipation pattern layer.Type: ApplicationFiled: August 30, 2019Publication date: November 26, 2020Inventors: Myung Sam KANG, Yong Koon LEE, Young Gwan KO, Young Chan KO, Moon Il KIM
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Publication number: 20200135654Abstract: A semiconductor package includes a core structure having a first through-hole and including a frame having an opening, a passive component disposed in the opening, a first encapsulant covering the frame and the passive component, a first metal layer disposed on an inner surface of the first through-hole, and a second metal layer disposed on an inner surface of the opening; a first semiconductor chip disposed in the first through-hole and having a first connection pad; a second encapsulant covering the core structure and the first semiconductor chip; a connection structure disposed on the core structure and the first semiconductor chip and including a redistribution layer; and a metal pattern layer disposed on the second encapsulant. The first and second metal layers are connected to the metal pattern layer through first and second metal vias having heights different from each other.Type: ApplicationFiled: September 13, 2019Publication date: April 30, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Koon LEE, Myung Sam Kang, Young Gwan Ko, Young Chan Ko, Chang Bae Lee
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Patent number: 8114771Abstract: A semiconductor wafer scale package system is provided including providing a semiconductor substrate having a through-hole via with a conductive coating, forming a filled via by filling the through-hole via with a conductive material, coupling a package substrate to the filled via, and singulating a chip scale package from the semiconductor substrate and the package substrate.Type: GrantFiled: December 22, 2006Date of Patent: February 14, 2012Assignee: STATS ChipPAC Ltd.Inventors: Hyung Jun Jeon, Tae Keun Lee, Young Chan Ko
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Patent number: 7364639Abstract: A method of forming twisted, curly fibers from a wet wood pulp without the aid of a wet fluffing process or a chemical cross-linker. The method includes forming the wet wood pulp into fiber bundles and subsequently thermally drying the fiber bundles. The invention also includes curly fibers derived from the method of the invention.Type: GrantFiled: August 29, 2005Date of Patent: April 29, 2008Assignee: Kimberly-Clark Worldwide, Inc.Inventors: Sheng-Hsin Hu, Young Chan Ko
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Publication number: 20070164422Abstract: A semiconductor wafer scale package system is provided including providing a semiconductor substrate having a through-hole via with a conductive coating, forming a filled via by filling the through-hole via with a conductive material, coupling a package substrate to the filled via, and singulating a chip scale package from the semiconductor substrate and the package substrate.Type: ApplicationFiled: December 22, 2006Publication date: July 19, 2007Applicant: STATS ChipPAC LTD.Inventors: Hyung Jun Jeon, Tae Keun Lee, Young Chan Ko
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Patent number: 6984447Abstract: A method of forming twisted, curly fibers from a wet wood pulp without the aid of a wet fluffing process or a chemical cross-linker. The method includes forming the wet wood pulp into fiber bundles and subsequently thermally drying the fiber bundles. The invention also includes curly fibers derived from the method of the invention.Type: GrantFiled: December 26, 2002Date of Patent: January 10, 2006Assignee: Kimberly-Clark Worldwide, Inc.Inventors: Sheng-Hsin Hu, Young Chan Ko
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Patent number: 6837970Abstract: A method of modifying a two-dimensional, flat fiber morphology of a never-been-dried wood pulp into a three-dimensional twisted fiber morphology without the aid of a chemical cross-linker. The method includes the steps of treating a never-been-dried wood pulp fiber slurry with a drying aid and thermally drying the wood pulp fiber slurry. The method may alternatively, or additionally, include the steps of spray drying a wood pulp fiber slurry and/or a slurry of a hydrophilic material, and flash drying the spray dried wood pulp fiber slurry and/or slurry of hydrophilic material.Type: GrantFiled: December 18, 2001Date of Patent: January 4, 2005Assignee: Kimberly-Clark Worldwide, Inc.Inventors: Young Chan Ko, Sheng-Hsin Hu, Kambiz B. Makoui
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Publication number: 20040203308Abstract: A process for making an absorbent material involves flash-drying a superabsorbent polymer precursor composition. The process may be used to make a superabsorbent-fiber material without the necessity of mixing conventional superabsorbent solid particles with pulp fluff is provided. The synthesis (i.e., polymerization) of the superabsorbent is completely integrated into the process for forming the absorbent material. One or more streams of superabsorbent polymer precursor composition are provided, to which a plurality of individual fibers may be added. The resulting in-situ polymerized superabsorbent-fiber material is then flash-dried and can subsequently be formed into a superabsorbent-fiber composite. The flash-drying is relatively inexpensive and requires little drying time compared to conventional drying methods.Type: ApplicationFiled: April 9, 2003Publication date: October 14, 2004Inventors: Young Chan Ko, Stanley R. Kellenberger, Kambiz Bayat Makoui
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Publication number: 20040204554Abstract: A process for making a multifunctional superabsorbent polymer, and for making an absorbent structure containing superabsorbent polymer. The synthesis (i.e., polymerization) of the superabsorbent is completely integrated into the process for forming the multifunctional superabsorbent polymer and/or absorbent structure. More particularly, a monomer solution containing an oxidizing agent, a monomer solution containing a reducing agent, and at least one functional additive are combined to form the multifunctional superabsorbent polymer. A valve can be used to control the liquid drop sizes of the monomer solutions as well as of the oxidizing agent, reducing agent, and functional additive(s). The droplets can be collected on a substrate, resulting in the formation of an absorbent structure.Type: ApplicationFiled: April 9, 2003Publication date: October 14, 2004Inventors: Young Chan Ko, Stanley R. Kellenberger, Lee Kirby Jameson, Varunesh Sharma
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Publication number: 20040127869Abstract: A method of forming twisted, curly fibers from a wet wood pulp without the aid of a wet fluffing process or a chemical cross-linker. The method includes forming the wet wood pulp into fiber bundles and subsequently thermally drying the fiber bundles. The invention also includes curly fibers derived from the method of the invention.Type: ApplicationFiled: December 26, 2002Publication date: July 1, 2004Inventors: Sheng-Hsin Hu, Young Chan Ko
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Publication number: 20030111193Abstract: A method of modifying a two-dimensional, flat fiber morphology of a never-been-dried wood pulp into a three-dimensional twisted fiber morphology without the aid of a chemical cross-linker. The method includes the steps of treating a never-been-dried wood pulp fiber slurry with a drying aid and thermally drying the wood pulp fiber slurry. The method may alternatively, or additionally, include the steps of spray drying a wood pulp fiber slurry and/or a slurry of a hydrophilic material, and flash drying the spray dried wood pulp fiber slurry and/or slurry of hydrophilic material.Type: ApplicationFiled: December 18, 2001Publication date: June 19, 2003Inventors: Young Chan Ko, Sheng-Hsin Hu, Kambiz B. Makoui
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Patent number: 6525109Abstract: The present invention relates to a process of preparing polycarbonate, more specifically to a process of preparing polycarbonates by solid state polymerization using microwave radiation, which comprises steps of preparing polycarbonate prepolymer having a certain range of viscosity average molecular weight; converting said polycarbonate prepolymer into crystalline particles having a certain degree of crystallinity; and producing polycarbonates by solid state polymerization of said crystalline particles by applying microwave radiation, thus resulting in production of high quality polycarbonates with high molecular weight within short time.Type: GrantFiled: July 13, 2001Date of Patent: February 25, 2003Assignees: Korea Research Institute of Chemical Technology, S-Oil CorporationInventors: Kil-Yeong Choi, Jae Heung Lee, Young Chan Ko, Il Seok Choi, Cheol-Hyun Kim, Kwang Soo Yoon, Kyong Soon Lee