Abstract: A power semiconductor device includes a drift layer of a first conductivity-type on a first conductivity-type substrate, a plurality of well regions of a second conductivity-type on the drift layer, a plurality of source regions of a first conductivity-type respectively disposed on the plurality of well regions, the plurality of well regions and the plurality of source regions comprise stacks having rounded sides, a gate electrode surrounding the stacks and filled a space between the stacks, a gate insulating layer between the stacks and the gate electrode, an interlayer insulating layer on the gate electrode, a source electrode on the interlayer insulating layer and having a plurality of contact portions extending from upper surfaces of the plurality of source regions to the plurality of well regions, and a drain electrode on the bottom of the substrate.

Abstract: A semiconductor device has a substrate. A first electrical component and second electrical component are disposed over the substrate. A conductive pillar is formed over the substrate between the first electrical component and second electrical component. A first shielding layer is formed over the first electrical component and conductive pillar by jet printing conductive material. A second shielding layer is formed over the first electrical component and second electrical component by sputtering, spraying, or plating conductive material. An insulating layer is optionally formed between the first shielding layer and second shielding layer by jet printing insulating material over the first shielding layer.

Abstract: A power semiconductor device includes a substrate having a first conductivity type and being provided with a drift layer having the first conductivity type; a well region having a second conductivity type; source regions having the first conductivity type; gate insulating layers in gate trenches penetrating the source regions and the well region and including a high-K material; gate electrodes on the gate insulating layers and including a metal material; a gate bus line connected to ends of the gate electrodes; a gate pad spaced apart from the gate bus line; a connector electrically connecting the gate bus line to the gate pad and including a material having a resistivity greater than those of the gate bus line and the gate pad; a dielectric layer on the gate electrodes, the gate bus line, the gate pad, and the connector; and a drain electrode on a lower surface of the substrate.

Abstract: A power semiconductor device includes a substrate of a first conductivity-type, a drift layer of the first conductivity-type, a well region of a second conductivity-type on the drift layer, a source region of the first conductivity-type on the well region, a gate insulating layer in a gate trench penetrating through the source region and the well region, a gate electrode on the gate insulating layer within the gate trench, a dielectric layer on the gate electrode, a source electrode in contact with the dielectric layer, the well region, and the source region, and a drain electrode on a lower surface of the substrate, wherein a side surface of the dielectric layer is coplanar with a side surface of the gate electrode, and the source region and the well region form a structure that is partially recessed from an upper surface thereof in regions in contact with the source electrode to have inclined surfaces.

Abstract: A power semiconductor device includes a substrate having a first conductivity-type. A drift layer is on the substrate and has the first conductivity-type. A well region is on the drift layer and has a second conductivity-type. A source region is on the well region and has the first conductivity-type. A gate electrode is in a gate trench penetrating the source region and the well region. A gate insulating layer is between the gate electrode and the well region. A drain electrode is on a lower surface of the substrate. A lower surface of the gate electrode has a first width and an upper surface has a second width greater than the first width. A side surface of the gate electrode has a step portion where a width of the gate electrode changes. The step portion is positioned at a lower level than a lower surface of the source region.

Abstract: A power semiconductor device includes a substrate; a drift layer on the substrate; a well region extending from an upper surface of the drift layer into the drift layer; a source region extending from an upper surface of the well region into the well region; a gate electrode on the drift layer and the well region; a gate insulating layer between the gate electrode and the well region; an isolation insulating layer in an isolation trench extending from the upper surface of the drift layer into the drift layer below the gate electrode; a dielectric layer covering the gate electrode and the source region; and a drain electrode on a lower surface of the substrate. The gate insulating layer, the isolation insulating layer, and the dielectric layer are configured to apply tensile stress to at least a portion of the well region.

Abstract: A semiconductor package including a first redistribution structure, a second redistribution structure disposed on the first redistribution structure, a semiconductor chip disposed on an upper surface of the second redistribution structure, a bridge chip disposed on a lower surface of the second redistribution structure, a molding layer disposed between the first redistribution structure and the second redistribution structure, where the molding layer surrounds the bridge chip, and a stiffener disposed on the upper surface of the second redistribution structure. The stiffener includes an opening. The semiconductor chip is disposed in the opening of the stiffener.

Abstract: A semiconductor device has an interposer. A first semiconductor die with a photonic portion is disposed over the interposer. The photonic portion extends outside a footprint of the interposer. The interposer and first semiconductor die are disposed over a substrate. An encapsulant is deposited between the interposer and substrate. The photonic portion remains exposed from the encapsulant.

Abstract: A semiconductor device has an electrical component and a first TIM with a first compliant property is disposed over a surface of the electrical component. A second TIM having a second compliant property greater than the first compliant property is disposed over the surface of the electrical component within the first TIM. A third TIM can be disposed over the surface of the electrical component along the first TIM. A heat sink is disposed over the first TIM and second TIM. The second TIM has a shape of a star pattern, grid of dots, parallel lines, serpentine, or concentric geometric shapes. The first TIM provides adhesion for joint reliability and the second TIM provides stress relief. Alternatively, a heat spreader is disposed over the first TIM and second TIM and a heat sink is disposed over a third TIM and fourth TIM on the heat spreader.

Abstract: A semiconductor device has a substrate and a first electrical component disposed over a first surface of the substrate. An RF antenna interposer is disposed over the substrate with the first electrical component connected to a first antenna disposed on a surface of the antenna interposer. An area of the antenna interposer is substantially the same as an area of the substrate. The first antenna disposed on the surface of the antenna interposer has a plurality of islands of conductive material. Alternatively, the first antenna disposed on the surface of the antenna interposer has a spiral shape of conductive material. A second antenna can be disposed on the surface of the antenna interposer connected to a second electrical component disposed over the substrate. A second electrical component can be disposed over a second surface of the substrate opposite the first surface of the substrate.

Abstract: A semiconductor device has a substrate and a plurality of bond wires is disposed in a pattern across on the substrate. The pattern of bond wires can be a plurality of rows of bond wires. A plurality of electrical components is disposed over the substrate as an SIP module. An encapsulant is deposited over the substrate, electrical components, and bond wire. An opening is formed in the encapsulant extending to the bond wire. The opening can be a trench extending across the bond wires disposed on the substrate, or a plurality of openings individually exposing each of a plurality of bond wires. A conductive material is disposed in the opening. A shielding layer is formed over the encapsulant and in contact with the conductive material. The shielding layer, conductive material, and bond wires reduce the effects of EMI, RFI, and other inter-device interference.

Abstract: A semiconductor device has a semiconductor die with a sensitive area. A dam wall is formed over the semiconductor die proximate to the sensitive area. In one embodiment, the dam wall has a vertical segment and side wings. The dam wall can have a plurality of rounded segments integrated with a plurality of vertical segments as a unitary body. Alternatively, the dam wall has a plurality of separate vertical segments arranged in two or more overlapping rows. A plurality of conductive posts is formed over the semiconductor die. An electrical component is disposed over the semiconductor die. The semiconductor die and electrical component are disposed over a substrate. An insulating layer is formed over the substrate outside the dam wall. An underfill material is deposited between the semiconductor die and substrate. The dam wall and insulating layer inhibit the underfill material from contacting any portion of the sensitive area.

Abstract: A semiconductor device has a substrate. A first electrical component and second electrical component are disposed over the substrate. A conductive pillar is formed over the substrate between the first electrical component and second electrical component. A first shielding layer is formed over the first electrical component and conductive pillar by jet printing conductive material. A second shielding layer is formed over the first electrical component and second electrical component by sputtering, spraying, or plating conductive material. An insulating layer is optionally formed between the first shielding layer and second shielding layer by jet printing insulating material over the first shielding layer.

Abstract: A semiconductor device has an electrical component and a first TIM with a first compliant property is disposed over a surface of the electrical component. A second TIM having a second compliant property greater than the first compliant property is disposed over the surface of the electrical component within the first TIM. A third TIM can be disposed over the surface of the electrical component along the first TIM. A heat sink is disposed over the first TIM and second TIM. The second TIM has a shape of a star pattern, grid of dots, parallel lines, serpentine, or concentric geometric shapes. The first TIM provides adhesion for joint reliability and the second TIM provides stress relief. Alternatively, a heat spreader is disposed over the first TIM and second TIM and a heat sink is disposed over a third TIM and fourth TIM on the heat spreader.

Abstract: A semiconductor device has a substrate and a first electrical component disposed over a first surface of the substrate. An RF antenna interposer is disposed over the substrate with the first electrical component connected to a first antenna disposed on a surface of the antenna interposer. An area of the antenna interposer is substantially the same as an area of the substrate. The first antenna disposed on the surface of the antenna interposer has a plurality of islands of conductive material. Alternatively, the first antenna disposed on the surface of the antenna interposer has a spiral shape of conductive material. A second antenna can be disposed on the surface of the antenna interposer connected to a second electrical component disposed over the substrate. A second electrical component can be disposed over a second surface of the substrate opposite the first surface of the substrate.

Abstract: An electric motor including a tension member is proposed. The electric motor includes the tension member installed therein and composed of step parts stacked in multiple steps, so that structural strength and structural robustness are improved.

Abstract: A semiconductor device has a substrate and a first electrical component disposed over a first surface of the substrate. An RF antenna interposer is disposed over the substrate with the first electrical component connected to a first antenna disposed on a surface of the antenna interposer. An area of the antenna interposer is substantially the same as an area of the substrate. The first antenna disposed on the surface of the antenna interposer has a plurality of islands of conductive material. Alternatively, the first antenna disposed on the surface of the antenna interposer has a spiral shape of conductive material. A second antenna can be disposed on the surface of the antenna interposer connected to a second electrical component disposed over the substrate. A second electrical component can be disposed over a second surface of the substrate opposite the first surface of the substrate.

Abstract: A semiconductor device has an electrical component and a first TIM with a first compliant property is disposed over a surface of the electrical component. A second TIM having a second compliant property greater than the first compliant property is disposed over the surface of the electrical component within the first TIM. A third TIM can be disposed over the surface of the electrical component along the first TIM. A heat sink is disposed over the first TIM and second TIM. The second TIM has a shape of a star pattern, grid of dots, parallel lines, serpentine, or concentric geometric shapes. The first TIM provides adhesion for joint reliability and the second TIM provides stress relief. Alternatively, a heat spreader is disposed over the first TIM and second TIM and a heat sink is disposed over a third TIM and fourth TIM on the heat spreader.

Abstract: Proposed is a motor having a flux ring in which the flux ring is fastened to a flux ring fastening part formed along the circumferential surface of a yoke.

Abstract: A semiconductor device has an interposer. A first semiconductor die with a photonic portion is disposed over the interposer. The photonic portion extends outside a footprint of the interposer. The interposer and first semiconductor die are disposed over a substrate. An encapsulant is deposited between the interposer and substrate. The photonic portion remains exposed from the encapsulant.