Patents by Inventor Youngcheon Kwon
Youngcheon Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250169067Abstract: A semiconductor device includes a semiconductor structure including a semiconductor substrate having an active zone with a channel; a through silicon via (TSV) structure including a power TSV configured to transmit power and a signal TSV configured to transmit a signal; and a keep-out zone located a predetermined distance away from the TSV structure and bounded by the active zone. The TSV structure penetrates the semiconductor substrate. The keep-out zone includes a first element area a first distance away from the power TSV, and a second element area a second distance away from the signal TSV.Type: ApplicationFiled: January 17, 2025Publication date: May 22, 2025Inventors: JAESAN KIM, SEUNGHAN WOO, HAESUK LEE, YOUNGCHEON KWON, REUM OH
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Patent number: 12250807Abstract: A semiconductor device includes a semiconductor structure including a semiconductor substrate having an active zone with a channel; a through silicon via (TSV) structure including a power TSV configured to transmit power and a signal TSV configured to transmit a signal; and a keep-out zone located a predetermined distance away from the TSV structure and bounded by the active zone. The TSV structure penetrates the semiconductor substrate. The keep-out zone includes a first element area a first distance away from the power TSV, and a second element area a second distance away from the signal TSV.Type: GrantFiled: October 7, 2021Date of Patent: March 11, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jaesan Kim, Seunghan Woo, Haesuk Lee, Youngcheon Kwon, Reum Oh
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Publication number: 20240282353Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.Type: ApplicationFiled: May 3, 2024Publication date: August 22, 2024Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Youngcheon KWON, Jemin Ryu, Jaeyoun Youn, Haesuk Lee, Jihyun Choi
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Patent number: 12001699Abstract: A memory device according to an aspect may include a memory cell array including a first bank region and a second bank region each including a plurality of banks; an operation logic including one or more first processing elements (PEs) corresponding to the first bank region and one or more second PEs corresponding to the second bank region; a control logic configured to control modes of the first bank region and the second bank region based on externally sourced setting information; first and second mode signal generators configured to control enabling the first PEs, wherein the first mode signal generator is configured to output the first mode signal to enable the first PEs and the second mode signal generator is configured to output the second mode signal to disable the second PEs responsive to the first bank region being set to an operation mode and the second bank region being set to a normal mode.Type: GrantFiled: December 22, 2022Date of Patent: June 4, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Youngcheon Kwon, Jaesan Kim, Jemin Ryu, Jaeyoun Youn, Haesuk Lee
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Patent number: 12002543Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.Type: GrantFiled: April 12, 2023Date of Patent: June 4, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Youngcheon Kwon, Jemin Ryu, Jaeyoun Youn, Haesuk Lee, Jihyun Choi
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Patent number: 11869571Abstract: A memory device including: a plurality of pins for receiving control signals from an external device; a first bank having first memory cells, wherein the first bank is activated in a first operation mode and a second operation mode; a second bank having second memory cells, wherein the second bank is deactivated in the first operation mode and activated in the second operation mode; a processing unit configured to perform an operation on first data, output from the first memory cells, and second data, output from the second memory cells, in the second operation mode; and a processing-in-memory (PIM) mode controller configured to select mode information, indicating one of the first operation mode and the second operation mode, in response to the control signals and to control at least one memory parameter, at least one mode register set (MRS) value, or a refresh mode according to the mode information.Type: GrantFiled: August 30, 2022Date of Patent: January 9, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Youngcheon Kwon, Jaeyoun Youn, Namsung Kim, Kyomin Sohn, Seongil O, Sukhan Lee
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Publication number: 20230245690Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.Type: ApplicationFiled: April 12, 2023Publication date: August 3, 2023Applicant: SAMSUNG ELECTRONCICS CO., LTD.Inventors: Youngcheon KWON, Jemin Ryu, Jaeyoun Youn, Haesuk Lee, Jihyun Choi
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Patent number: 11664061Abstract: A memory device according to some aspects of the inventive concepts includes a memory cell array including a plurality of banks, at least one Processing Element (PE) connected to at least one bank selected from the plurality of banks, and a control logic configured to control an active operation in which wordlines included in each of the plurality of banks is activated, and configured to control a refresh operation in which at least one bank is refreshed, based on a PE enable signal configured to selectively enable the at least one PE.Type: GrantFiled: April 18, 2022Date of Patent: May 30, 2023Inventors: Youngcheon Kwon, Sanghyuk Kwon, Kyomin Sohn, Jaeyoun Youn, Haesuk Lee
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Publication number: 20230138048Abstract: A memory device according to an aspect may include a memory cell array including a first bank region and a second bank region each including a plurality of banks; an operation logic including one or more first processing elements (PEs) corresponding to the first bank region and one or more second PEs corresponding to the second bank region; a control logic configured to control modes of the first bank region and the second bank region based on externally sourced setting information; first and second mode signal generators configured to control enabling the first PEs, wherein the first mode signal generator is configured to output the first mode signal to enable the first PEs and the second mode signal generator is configured to output the second mode signal to disable the second PEs responsive to the first bank region being set to an operation mode and the second bank region being set to a normal mode.Type: ApplicationFiled: December 22, 2022Publication date: May 4, 2023Inventors: Youngcheon Kwon, Jaesan Kim, Jemin Ryu, Jaeyoun Youn, Haesuk Lee
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Patent number: 11636885Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.Type: GrantFiled: January 12, 2022Date of Patent: April 25, 2023Assignee: SAMSUNG ELECTRONICS CO.. LTD.Inventors: Youngcheon Kwon, Jemin Ryu, Jaeyoun Youn, Haesuk Lee, Jihyun Choi
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Patent number: 11599301Abstract: A semiconductor memory device includes an interface semiconductor die, at least one memory semiconductor die, and through-silicon vias connecting the interface semiconductor die and the memory semiconductor die. The interface semiconductor die includes command pins to receive command signals transferred from a memory controller and an interface command decoder to decode the command signals. The memory semiconductor die includes a memory integrated circuit configured to store data and a memory command decoder to decode the command signals transferred from the interface semiconductor die. The interface semiconductor die does not include a clock enable pin to receive a clock enable signal from the memory controller. The interface and memory command decoders generate interface and memory clock enable signals to control clock supply with respect to the interface and memory semiconductor dies based on a power mode command transferred through the plurality of command pins from the memory controller.Type: GrantFiled: April 30, 2021Date of Patent: March 7, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Haesuk Lee, Reum Oh, Youngcheon Kwon, Beomyong Kil, Jemin Ryu, Jihyun Choi
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Patent number: 11561711Abstract: A memory device according to an aspect may include a memory cell array including a first bank region and a second bank region each including a plurality of banks; an operation logic including one or more first processing elements (PEs) corresponding to the first bank region and one or more second PEs corresponding to the second bank region; a control logic configured to control modes of the first bank region and the second bank region based on externally sourced setting information; first and second mode signal generators configured to control enabling the first PEs, wherein the first mode signal generator is configured to output the first mode signal to enable the first PEs and the second mode signal generator is configured to output the second mode signal to disable the second PEs responsive to the first bank region being set to an operation mode and the second bank region being set to a normal mode.Type: GrantFiled: June 1, 2021Date of Patent: January 24, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Youngcheon Kwon, Jaesan Kim, Jemin Ryu, Jaeyoun Youn, Haesuk Lee
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Publication number: 20220406369Abstract: A memory device including: a plurality of pins for receiving control signals from an external device; a first bank having first memory cells, wherein the first bank is activated in a first operation mode and a second operation mode; a second bank having second memory cells, wherein the second bank is deactivated in the first operation mode and activated in the second operation mode; a processing unit configured to perform an operation on first data, output from the first memory cells, and second data, output from the second memory cells, in the second operation mode; and a processing-in-memory (PIM) mode controller configured to select mode information, indicating one of the first operation mode and the second operation mode, in response to the control signals and to control at least one memory parameter, at least one mode register set (MRS) value, or a refresh mode according to the mode information.Type: ApplicationFiled: August 30, 2022Publication date: December 22, 2022Inventors: Youngcheon KWON, Jaeyoun YOUN, Namsung KIM, Kyomin SOHN, Seongil O, Sukhan LEE
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Patent number: 11462255Abstract: A memory device including: a plurality of pins for receiving control signals from an external device; a first bank having first memory cells, wherein the first bank is activated in a first operation mode and a second operation mode; a second bank having second memory cells, wherein the second bank is deactivated in the first operation mode and activated in the second operation mode; a processing unit configured to perform an operation on first data, output from the first memory cells, and second data, output from the second memory cells, in the second operation mode; and a processing-in-memory (PIM) mode controller configured to select mode information, indicating one of the first operation mode and the second operation mode, in response to the control signals and to control at least one memory parameter, at least one mode register set (MRS) value, or a refresh mode according to the mode information.Type: GrantFiled: April 26, 2021Date of Patent: October 4, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Youngcheon Kwon, Jaeyoun Youn, Namsung Kim, Kyomin Sohn, Seongil O, Sukhan Lee
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Patent number: 11416178Abstract: A memory device includes a memory bank including a plurality of banks, each including a memory cell array; a calculation logic including a plurality of processor-in-memory (PIM) circuits arranged in correspondence to the banks, each of the plurality of PIM circuits performing calculation processing using at least one selected from data provided from a host and information read from a corresponding bank among the banks; and a control logic configured to control a memory operation on the memory bank in response to a command and/or an address, each received from the host, or to control the calculation logic to perform the calculation processing, wherein reading operations are respectively performed in parallel on the banks for the calculation processing, offsets having different values are respectively configured for the banks, and information is read from different positions in respective memory cell arrays of the banks and provided to the PIM circuits.Type: GrantFiled: September 8, 2020Date of Patent: August 16, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyunsung Shin, Sanghyuk Kwon, Youngcheon Kwon, Sukhan Lee, Haesuk Lee
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Publication number: 20220238148Abstract: A memory device according to some aspects of the inventive concepts includes a memory cell array including a plurality of banks, at least one Processing Element (PE) connected to at least one bank selected from the plurality of banks, and a control logic configured to control an active operation in which wordlines included in each of the plurality of banks is activated, and configured to control a refresh operation in which at least one bank is refreshed, based on a PE enable signal configured to selectively enable the at least one PE.Type: ApplicationFiled: April 18, 2022Publication date: July 28, 2022Inventors: YOUNGCHEON KWON, SANGHYUK KWON, KYOMIN SOHN, JAEYOUN YOUN, HAESUK LEE
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Patent number: 11335392Abstract: A memory device according to some aspects of the inventive concepts includes a memory cell array including a plurality of banks, at least one Processing Element (PE) connected to at least one bank selected from the plurality of banks, and a control logic configured to control an active operation in which wordlines included in each of the plurality of banks is activated, and configured to control a refresh operation in which at least one bank is refreshed, based on a PE enable signal configured to selectively enable the at least one PE.Type: GrantFiled: June 16, 2020Date of Patent: May 17, 2022Inventors: Youngcheon Kwon, Sanghyuk Kwon, Kyomin Sohn, Jaeyoun Youn, Haesuk Lee
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Publication number: 20220139433Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.Type: ApplicationFiled: January 12, 2022Publication date: May 5, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Youngcheon Kwon, Jemin Ryu, Jaeyoun Youn, Haesuk Lee, Jihyun Choi
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Publication number: 20220130841Abstract: A semiconductor device includes a semiconductor structure including a semiconductor substrate having an active zone with a channel; a through silicon via (TSV) structure including a power TSV configured to transmit power and a signal TSV configured to transmit a signal; and a keep-out zone located a predetermined distance away from the TSV structure and bounded by the active zone. The TSV structure penetrates the semiconductor substrate. The keep-out zone includes a first element area a first distance away from the power TSV, and a second element area a second distance away from the signal TSV.Type: ApplicationFiled: October 7, 2021Publication date: April 28, 2022Inventors: Jaesan Kim, Seunghan Woo, Haesuk Lee, Youngcheon Kwon, Reum Oh
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Publication number: 20220083260Abstract: A semiconductor memory device includes an interface semiconductor die, at least one memory semiconductor die, and through-silicon vias connecting the interface semiconductor die and the memory semiconductor die. The interface semiconductor die includes command pins to receive command signals transferred from a memory controller and an interface command decoder to decode the command signals. The memory semiconductor die includes a memory integrated circuit configured to store data and a memory command decoder to decode the command signals transferred from the interface semiconductor die. The interface semiconductor die does not include a clock enable pin to receive a clock enable signal from the memory controller. The interface and memory command decoders generate interface and memory clock enable signals to control clock supply with respect to the interface and memory semiconductor dies based on a power mode command transferred through the plurality of command pins from the memory controller.Type: ApplicationFiled: April 30, 2021Publication date: March 17, 2022Inventors: Haesuk LEE, Reum OH, Youngcheon KWON, Beomyong KIL, Jemin RYU, Jihyun CHOI