Patents by Inventor YoungDal Roh

YoungDal Roh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10134664
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a dielectric core having an embedded pad; a top solder resist layer on the dielectric core, a pad top surface of the embedded pad below the top solder resist layer; a device interconnect attached to the embedded pad; and an integrated circuit device having an interconnect pillar, the interconnect pillar attached to the device interconnect for mounting the integrated circuit device to the dielectric core.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: November 20, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: MinKyung Kang, YoungDal Roh, Dong Ju Jeon, KyoungHee Park
  • Publication number: 20170162495
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a dielectric core having an embedded pad; a top solder resist layer on the dielectric core, a pad top surface of the embedded pad below the top solder resist layer; a device interconnect attached to the embedded pad; and an integrated circuit device having an interconnect pillar, the interconnect pillar attached to the device interconnect for mounting the integrated circuit device to the dielectric core.
    Type: Application
    Filed: February 15, 2017
    Publication date: June 8, 2017
    Inventors: MinKyung Kang, YoungDal Roh, Dong Ju Jeon, KyoungHee Park
  • Patent number: 9607938
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a dielectric core having an embedded pad; a top solder resist layer on the dielectric core, a pad top surface of the embedded pad below the top solder resist layer; a device interconnect attached to the embedded pad; and an integrated circuit device having an interconnect pillar, the interconnect pillar attached to the device interconnect for mounting the integrated circuit device to the dielectric core.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: March 28, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: MinKyung Kang, YoungDal Roh, Dong Ju Jeon, KyoungHee Park
  • Patent number: 9210816
    Abstract: A method of manufacture of a support system includes: forming a carrier having a detachable core and a carrier foil directly on the detachable core; forming a mask directly on the carrier foil, the mask having a mask hole through the mask; forming a bottom conductive layer within the mask hole and directly on the carrier foil; forming an interior insulation layer directly on the bottom conductive layer and the mask after the bottom conductive layer is formed within the mask hole; partially removing the interior insulation layer leaving an insulation hole through the interior insulation layer; forming a conductive connector completely within the insulation hole; and forming a bottom exterior insulation layer over the bottom conductive layer and the mask.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: December 8, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: YoungDal Roh, KyoungHee Park, Dong Ju Jeon, HyungSang Park
  • Patent number: 9171795
    Abstract: An integrated circuit packaging system, and a method of manufacture of an integrated circuit packaging system thereof, including: an embedding material on a component; a mask layer on the embedding material; a buried pattern in the mask layer, the outer surface of the buried pattern coplanar with the outer surface of the mask layer, the buried pattern electrically connected to the component; a patterned dielectric on a portion of the buried pattern; and an integrated circuit die on the buried pattern.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: October 27, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Dong Ju Jeon, KyoungHee Park, YoungDal Roh, JinHee Jung
  • Patent number: 9171739
    Abstract: An integrated circuit packaging system, and a method of manufacture thereof, including: a patterned first conductive plating; a molding on the patterned first conductive plating; a through via through the molding; a second conductive plating on the molding and the through via; a protection layer partially covering the first conductive plating, the second conductive plating and the molding; a device on the first conductive plating; and an external connector being attached to the second conductive plating.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: October 27, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: YoungDal Roh, DeokKyung Yang, HeeSoo Lee
  • Publication number: 20150171002
    Abstract: An integrated circuit packaging system, and a method of manufacture of an integrated circuit packaging system thereof, including: an embedding material on a component; a mask layer on the embedding material; a buried pattern in the mask layer, the outer surface of the buried pattern coplanar with the outer surface of the mask layer, the buried pattern electrically connected to the component; a patterned dielectric on a portion of the buried pattern; and an integrated circuit die on the buried pattern.
    Type: Application
    Filed: December 1, 2014
    Publication date: June 18, 2015
    Inventors: Dong Ju Jeon, KyoungHee Park, YoungDal Roh, JinHee Jung
  • Patent number: 8975665
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a first metal layer on a carrier; forming an insulation layer directly on the first metal layer; exposing a portion of the first metal layer for directly attaching to a die interconnect connecting to an integrated circuit; forming a second metal layer directly on the insulation layer opposite the side of the insulation layer exposed by removing the carrier; and forming a protective layer directly on the insulation layer and the second metal layer, the protective layer exposing a portion of the second metal layer for directly attaching an external interconnect.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: March 10, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: JinHee Jung, YoungDal Roh, KyoungHee Park
  • Publication number: 20150001705
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a dielectric core having an embedded pad; a top solder resist layer on the dielectric core, a pad top surface of the embedded pad below the top solder resist layer; a device interconnect attached to the embedded pad; and an integrated circuit device having an interconnect pillar, the interconnect pillar attached to the device interconnect for mounting the integrated circuit device to the dielectric core.
    Type: Application
    Filed: June 27, 2013
    Publication date: January 1, 2015
    Inventors: MinKyung Kang, YoungDal Roh, Dong Ju Jeon, KyoungHee Park
  • Publication number: 20140097475
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a first metal layer on a carrier; forming an insulation layer directly on the first metal layer; exposing a portion of the first metal layer for directly attaching to a die interconnect connecting to an integrated circuit; forming a second metal layer directly on the insulation layer opposite the side of the insulation layer exposed by removing the carrier; and forming a protective layer directly on the insulation layer and the second metal layer, the protective layer exposing a portion of the second metal layer for directly attaching an external interconnect.
    Type: Application
    Filed: January 16, 2013
    Publication date: April 10, 2014
    Inventors: JinHee Jung, YoungDal Roh, KyoungHee Park