Abstract: Disclosed is an ultra-wide band (UWB) radar device including a first antenna circuit including a first transmission circuit, a first reception circuit, a first oscillator that supplies a first clock signal to the first transmission circuit and the first reception circuit, and a first frequency counter, a second antenna circuit including a second transmission circuit, a second reception circuit, a second oscillator that supplies a second clock signal to the second transmission circuit and the second reception circuit, and a second frequency counter, and a controller that detects the target. The controller corrects a frequency error between the first clock signal and the second clock signal and compensates for a synchronization error between the first antenna circuit and the second antenna circuit.

Abstract: A semiconductor chip including a body that having a front surface and a rear surface; a wiring structure above the front surface of the body; a through via penetrating the body, and the through via is connected to the wiring structure; a heat dissipation structure above the rear surface of the body, and the heat dissipation structure includes a conductive layer connected to the through via; and a signal pad and a heat dissipation pad on the heat dissipation structure, and the signal pad and the heat dissipation pad are connected to the conductive layer.

Abstract: An apparatus for receiving a strobe signal may include an amplifier for amplifying a strobe signal input thereto, an offset generator for controlling the setting of a threshold for detecting a preamble signal by generating an offset for the amplifier, and a preamble detector for detecting a first preamble signal occurring at a point at which the amplified strobe signal is equal to or greater than the threshold and turning off the offset generator when the first preamble signal is detected.

Abstract: Disclosed is a receiver of a radar device, which includes a sampling circuit that receives a reflected pulse signal having a first period reflected from a detection target and samples the reflected pulse signal as a first received signal in response to a clock signal having a second period equal to the first period, an integration circuit that, in response to the clock signal, generates an analog integration signal based on the first received signal and a control signal, a comparison circuit that, in response to the clock signal, adjusts a count value and the control signal based on a result of comparing the analog integration signal with a reference signal and outputs the control signal to the integration circuit, and an ADC circuit that converts the analog integration signal into a digital integration signal.

Abstract: A semiconductor package according to an embodiment includes a connection substrate, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip is disposed on the connection substrate and includes a first interconnection area facing the connection substrate. The second semiconductor chip is disposed on the connection substrate and includes a second interconnection area facing the connection substrate. The second semiconductor chip includes a first edge adjacent to the first semiconductor chip and a second edge opposite to the first edge in a first direction. A first distance between the second interconnection area and the first edge in the first direction is different from a second distance between the second interconnection area and the second edge in the first direction.

Abstract: Disclosed herein are a duty cycle monitoring method and apparatus for a memory interface, including receiving a clock signal as input and generating a first delay time offset and a second delay time offset, receiving the clock signal and the first delay time offset and then outputting a first delayed signal, receiving the first delayed signal and the second delay time offset and then outputting a second delayed signal, receiving the clock signal and the second delayed signal and then outputting a delay value corresponding to a half-period of the clock signal, and monitoring, based on the first delayed signal, whether a duty cycle of the clock signal conforms to a duty cycle specification.

Abstract: A semiconductor package includes: a first base chip including a plurality of first vias; a chip stack disposed on the first base chip; and a second base chip disposed between the first base chip and the chip stack, wherein the second base chip includes a plurality of second vias, wherein the chip stack includes memory chips that are stacked on the second base chip, wherein each of the memory chips includes a plurality of third vias, and wherein the first base chip and the second base chip are logic chips.

Abstract: A semiconductor package may include vertically-stacked semiconductor chips and first, second, and third connection terminals connecting the semiconductor chips to each other. Each of the semiconductor chips may include a semiconductor substrate, an interconnection layer on the semiconductor substrate, penetration electrodes connected to the interconnection layer through the semiconductor substrate, and first, second, and third groups on the interconnection layer. The interconnection layer may include an insulating layer and first and second metal layers in the insulating layer. The first and second groups may be in contact with the second metal layer, and the third group may be spaced apart from the second metal layer. Each of the first and third groups may include pads connected to a corresponding one of the first and third connection terminals in a many-to-one manner. The second group may include pads connected to the second connection terminal in a one-to-one manner.

Abstract: A semiconductor package includes a first semiconductor chip. A second semiconductor chip is disposed on the first semiconductor chip. A bump structure is disposed between the first semiconductor chip and the second semiconductor chip. The bump structure electrically connects the first semiconductor chip and the second semiconductor chip to each other. The bump structure includes a first bump pad and a second bump pad disposed on a same plane as each other, and a solder bump disposed between the first bump pad and the second bump pad. The solder bump abuts on a side of the first bump pad and a side of the second bump pad.

Abstract: Provided are a novel polypeptide having endolysin activity, a fusion protein comprising the polypeptide and an antibiotic active protein, and an antibiotic use against a gram-negative pathogen of the polypeptide and/or fusion protein and/or a use for prevention and/or treatment of gram-negative pathogen infection and/or disease or symptoms related to gram negative pathogen infection.

Abstract: This application relates to an adsorption desalination system using a multi-effect evaporator apparatus. In one aspect, the system includes a multi-effect evaporator apparatus producing high-pressure vapor and low-pressure vapor, a plurality of reaction units including an adsorbent adsorbing or desorbing moisture from the high-pressure vapor and low-pressure vapor and a heat exchange tube transferring heat to the adsorbent. The system may also include a condenser condensing vapor containing moisture desorbed from the adsorbents, and cold-hot water lines selectively supplying chilled water and hot water to the heat exchange tubes. The system may further include vapor lines connecting the multi-effect evaporator apparatus and the reaction units, and the reaction units and the condenser, respectively, valves disposed in the vapor lines, and a valve controller controlling operation of the valves to selectively supply chilled water or hot water supplied to the heat exchange tubes from the cold-hot water lines.

Abstract: A semiconductor package may include vertically-stacked semiconductor chips and first, second, and third connection terminals connecting the semiconductor chips to each other. Each of the semiconductor chips may include a semiconductor substrate, an interconnection layer on the semiconductor substrate, penetration electrodes connected to the interconnection layer through the semiconductor substrate, and first, second, and third groups on the interconnection layer. The interconnection layer may include an insulating layer and first and second metal layers in the insulating layer. The first and second groups may be in contact with the second metal layer, and the third group may be spaced apart from the second metal layer. Each of the first and third groups may include pads connected to a corresponding one of the first and third connection terminals in a many-to-one manner. The second group may include pads connected to the second connection terminal in a one-to-one manner.

Abstract: Provided are a novel polypeptide having endolysin activity, a fusion protein comprising the polypeptide and an antibiotic active protein, and an antibiotic use against a gram-negative pathogen of the polypeptide and/or fusion protein and/or a use for prevention and/or treatment of gram-negative pathogen infection and/or disease or symptoms related to gram negative pathogen infection.

Abstract: This application relates to an adsorption desalination system using a multi-effect evaporator apparatus. In one aspect, the system includes a multi-effect evaporator apparatus producing high-temperature vapor and low-temperature vapor, a plurality of reaction units including an adsorbent adsorbing or desorbing moisture from the high-temperature vapor and low-temperature vapor and a heat exchange tube transferring heat to the adsorbent. The system may also include a condenser condensing vapor containing moisture desorbed from the adsorbents, and cold-hot water lines selectively supplying chilled water and hot water to the heat exchange tubes.

Abstract: A heat radiation device includes a semiconductor substrate. A first electrode is disposed on the semiconductor substrate. A second electrode is disposed on the semiconductor substrate and is spaced apart from the first electrode. A first through electrode is disposed in the semiconductor substrate. The first through electrode is electrically connected to the first electrode.

Abstract: An electronic device includes a substrate, a first electronic product arranged on the substrate, a second electronic product arranged on the substrate to be spaced apart from the first electronic product, and a heat dissipating assembly covering the first and second electronic products, the heat dissipating assembly comprising a heat dissipating chamber including a hermetically sealed space having a first portion having one or more gaps in which a flowable heat dissipation fluid is disposed and having a second portion in which a solid thermal conductive member is disposed to prevent the flow of the heat dissipation fluid across the second portion with respect to a plan view, wherein the first portion of the heat dissipating chamber has a first thermal conductivity and overlaps with the first electronic product in the plan view, wherein the solid thermal conductive member has a second thermal conductivity less than the first thermal conductivity, wherein the solid thermal conductive member overlaps with the se

Abstract: A heat radiation device includes a semiconductor substrate. A first electrode is disposed on the semiconductor substrate. A second electrode is disposed on the semiconductor substrate and is spaced apart from the first electrode. A first through electrode is disposed in the semiconductor substrate. The first through electrode is electrically connected to the first electrode.

Abstract: An electronic device includes a substrate, a first electronic product arranged on the substrate, a second electronic product arranged on the substrate to be spaced apart from the first electronic product, and a heat dissipating assembly covering the first and second electronic products, the heat dissipating assembly comprising a heat dissipating chamber including a hermetically sealed space having a first portion having one or more gaps in which a flowable heat dissipation fluid is disposed and having a second portion in which a solid thermal conductive member is disposed to prevent the flow of the heat dissipation fluid across the second portion with respect to a plan view, wherein the first portion of the heat dissipating chamber has a first thermal conductivity and overlaps with the first electronic product in the plan view, wherein the solid thermal conductive member has a second thermal conductivity less than the first thermal conductivity, wherein the solid thermal conductive member overlaps with the se

Abstract: A semiconductor device includes a semiconductor package and a mark. The semiconductor package includes a semiconductor chip including a hot spot from which heat is generated, and a mold layer encapsulating the semiconductor chip. The mark is disposed on the semiconductor package. The mark is formed in a region of the semiconductor package that corresponds to a position of the hot spot.

Abstract: A package substrate may include an insulating substrate, internal circuits and a warpage-suppressing member. The insulating substrate may have a plurality of mount regions in which semiconductor chips may be mounted, and a peripheral region. The internal circuits may be arranged in the mount regions. The warpage-suppressing member is different from the semiconductor chips and may be arranged in at least one of the mount regions to suppress a warpage of the insulating substrate. Thus, warpage of the package substrate may be suppressed during a reflow process.