Abstract: Provided is a memory system including a host system including a memory controller configured to control a read or write operation for a plurality of memory ranks, based on target or non-target information for the plurality of memory ranks, and a memory device including a storage configured to store on-die termination (ODT) information of the memory ranks. Here, the memory controller is further configured to determine a target rank to be read or written, and transmit information about the determined target rank, to the memory device, and the memory device is further configured to perform a comparison of the ODT information of the memory ranks stored in the storage with target or non-target information received from the memory controller, and change an ODT value of the target rank, based on target information received from the memory controller based on a result of the comparison.

Abstract: An input/output interface circuit includes a common receiving driver configured to receive a differential clock signal and output a first clock signal corresponding to the differential clock signal and a pair of sub-channels connected to the common receiving driver. Each sub-channel of the pair of sub-channels may be configured to receive the first clock signal and a chip select signal, output a second clock signal through a logical AND operation of the first clock signal and the chip select signal, and output a single clock signal, among the second clock signal and one or more divided clock signals. The single clock signal is used to sample a command address signal.

Abstract: A memory device includes a divide circuit configured to generate an internal data clock signal based on a data clock signal, wherein the data clock signal has a first voltage level for a first time period and toggles during a second time period consecutive to the first time period, a detect circuit configured to generate a feedback data corresponding to the first voltage level based on the internal data clock signal, and an input/output circuit configured to output the feedback data to an external device.

Abstract: There is provided a memory module including a first memory device constituting a first rank, and a second memory device constituting a second rank sharing a command/address signal and a clock signal with the first memory device. The first memory device and the second memory device receive the command/address signal and the clock signal in a matched type, and the first memory device includes a variable delay line for adjusting a delay of the received clock signal.

Abstract: A semiconductor package includes a memory die stack having a clock signal shared by lower and upper bytes. Each of a plurality of memory dies constituting the memory die stack of the semiconductor package includes a first clock circuit configured to generate a read clock signal for a lower byte and an upper byte constituting a data width of the memory die, and a plurality of first die bond pads corresponding to the number of ranks of a memory system including the memory die, and each of the plurality of first die bond pads is set for each rank. The first clock circuit is connected to, among the plurality of first die bond pads, a die bond pad corresponding to a rank to which the memory die belongs.

Abstract: A method of calibrating a signal level of a memory device includes performing pull-up code and pull-down code calibrations, using a ZQ calibration for non-return-to-zero (NRZ) signaling, performing a most significant bit (MSB) code calibration, using an MSB additional driver for pulse amplitude modulation level-4 (PAM4) signaling, and performing a least significant bit (LSB) code calibration using an LSB additional driver for the PAM4 signaling.

Abstract: Provided is a memory system including a host system including a memory controller configured to control a read or write operation for a plurality of memory ranks, based on target or non-target information for the plurality of memory ranks, and a memory device including a storage configured to store on-die termination (ODT) information of the memory ranks. Here, the memory controller is further configured to determine a target rank to be read or written, and transmit information about the determined target rank, to the memory device, and the memory device is further configured to perform a comparison of the ODT information of the memory ranks stored in the storage with target or non-target information received from the memory controller, and change an ODT value of the target rank, based on target information received from the memory controller based on a result of the comparison.

Abstract: A method of calibrating a signal level of a memory device includes performing pull-up code and pull-down code calibrations, using a ZQ calibration for non-return-to-zero (NRZ) signaling, performing a most significant bit (MSB) code calibration, using an MSB additional driver for pulse amplitude modulation level-4 (PAM4) signaling, and performing a least significant bit (LSB) code calibration using an LSB additional driver for the PAM4 signaling.

Abstract: A memory device includes a memory cell array and a transmitter, wherein the transmitter includes a pulse amplitude modulation (PAM) encoder configured to generate a PAM-n first input signal (where n is an integer greater than or equal to 4) from data read from the memory cell array; a pre-driver configured to generate a second input signal based on the first input signal and based on a calibration code signal, and output the second input signal using a first power voltage; and a driver configured to output a PAM-n DQ signal using a second power voltage lower than the first power voltage in response to the second input signal.

Abstract: A method of calibrating a signal level of a memory device includes performing pull-up code and pull-down code calibrations, using a ZQ calibration for non-return-to-zero (NRZ) signaling, performing a most significant bit (MSB) code calibration, using an MSB additional driver for pulse amplitude modulation level-4 (PAM4) signaling, and performing a least significant bit (LSB) code calibration using an LSB additional driver for the PAM4 signaling.

Abstract: A memory device includes a memory cell array and a transmitter, wherein the transmitter includes a pulse amplitude modulation (PAM) encoder configured to generate a PAM-n first input signal (where n is an integer greater than or equal to 4) from data read from the memory cell array; a pre-driver configured to generate a second input signal based on the first input signal and based on a calibration code signal, and output the second input signal using a first power voltage; and a driver configured to output a PAM-n DQ signal using a second power voltage lower than the first power voltage in response to the second input signal.